prev_cmp_mif1.tan.qmsg

存储示波器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "CNT10B:inst1\|CLKOUT~3 " "Info: Detected gated clock \"CNT10B:inst1\|CLKOUT~3\" as buffer" {  } { { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT10B:inst1\|CLKOUT~3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ADCINT:inst\|current_state.st4 " "Info: Detected ripple clock \"ADCINT:inst\|current_state.st4\" as buffer" {  } { { "ADCINT.vhd" "" { Text "C:/cunchuqi/ADCINT.vhd" 16 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ADCINT:inst\|current_state.st4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] memory ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0 204.08 MHz 4.9 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 204.08 MHz between source register \"CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination memory \"ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0\" (period= 4.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.300 ns + Longest register memory " "Info: + Longest register to memory delay is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC5_D16 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D16; Fanout = 19; REG Node = 'CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.800 ns) 2.300 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0 2 MEM EC10_D 1 " "Info: 2: + IC(1.500 ns) + CELL(0.800 ns) = 2.300 ns; Loc. = EC10_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns ( 34.78 % ) " "Info: Total cell delay = 0.800 ns ( 34.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 65.22 % ) " "Info: Total interconnect delay = 1.500 ns ( 65.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 1.500ns } { 0.000ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.900 ns - Smallest " "Info: - Smallest clock skew is -0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.500 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_126 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 7; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 16 -200 -32 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.600 ns) 3.700 ns CNT10B:inst1\|CLKOUT~3 2 COMB LC1_F9 177 " "Info: 2: + IC(0.100 ns) + CELL(1.600 ns) = 3.700 ns; Loc. = LC1_F9; Fanout = 177; COMB Node = 'CNT10B:inst1\|CLKOUT~3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { CLK CNT10B:inst1|CLKOUT~3 } "NODE_NAME" } } { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 6.500 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0 3 MEM EC10_D 1 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 6.500 ns; Loc. = EC10_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 55.38 % ) " "Info: Total cell delay = 3.600 ns ( 55.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 44.62 % ) " "Info: Total interconnect delay = 2.900 ns ( 44.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { CLK CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 0.000ns 0.100ns 2.800ns } { 0.000ns 2.000ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_126 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 7; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 16 -200 -32 32 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns ADCINT:inst\|current_state.st4 2 REG LC3_F9 11 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC3_F9; Fanout = 11; REG Node = 'ADCINT:inst\|current_state.st4'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK ADCINT:inst|current_state.st4 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "C:/cunchuqi/ADCINT.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 4.600 ns CNT10B:inst1\|CLKOUT~3 3 COMB LC1_F9 177 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 4.600 ns; Loc. = LC1_F9; Fanout = 177; COMB Node = 'CNT10B:inst1\|CLKOUT~3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 } "NODE_NAME" } } { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 7.400 ns CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 4 REG LC5_D16 19 " "Info: 4: + IC(2.800 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC5_D16; Fanout = 19; REG Node = 'CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 52.70 % ) " "Info: Total cell delay = 3.900 ns ( 52.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 47.30 % ) " "Info: Total interconnect delay = 3.500 ns ( 47.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.800ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { CLK CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 0.000ns 0.100ns 2.800ns } { 0.000ns 2.000ns 1.600ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.800ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.200 ns + " "Info: + Micro setup delay of destination is 1.200 ns" {  } { { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 1.500ns } { 0.000ns 0.800ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { CLK CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 0.000ns 0.100ns 2.800ns } { 0.000ns 2.000ns 1.600ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { CLK ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { CLK CLK~out ADCINT:inst|current_state.st4 CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 0.300ns 2.800ns } { 0.000ns 2.000ns 0.500ns 1.400ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "WREN register memory CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0 217.39 MHz Internal " "Info: Clock \"WREN\" Internal fmax is restricted to 217.39 MHz between source register \"CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination memory \"ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.3 ns 2.3 ns 4.6 ns " "Info: fmax restricted to Clock High delay (2.3 ns) plus Clock Low delay (2.3 ns) : restricted to 4.6 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.300 ns + Longest register memory " "Info: + Longest register to memory delay is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC5_D16 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D16; Fanout = 19; REG Node = 'CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.800 ns) 2.300 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0 2 MEM EC10_D 1 " "Info: 2: + IC(1.500 ns) + CELL(0.800 ns) = 2.300 ns; Loc. = EC10_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns ( 34.78 % ) " "Info: Total cell delay = 0.800 ns ( 34.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 65.22 % ) " "Info: Total interconnect delay = 1.500 ns ( 65.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 1.500ns } { 0.000ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WREN destination 13.600 ns + Shortest memory " "Info: + Shortest clock path from clock \"WREN\" to destination memory is 13.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns WREN 1 CLK PIN_8 9 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 9; CLK Node = 'WREN'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WREN } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 168 -264 -96 184 "WREN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.600 ns) 10.800 ns CNT10B:inst1\|CLKOUT~3 2 COMB LC1_F9 177 " "Info: 2: + IC(4.300 ns) + CELL(1.600 ns) = 10.800 ns; Loc. = LC1_F9; Fanout = 177; COMB Node = 'CNT10B:inst1\|CLKOUT~3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { WREN CNT10B:inst1|CLKOUT~3 } "NODE_NAME" } } { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 13.600 ns ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0 3 MEM EC10_D 1 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 13.600 ns; Loc. = EC10_D; Fanout = 1; MEM Node = 'ram8:inst2\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~reg_ra0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.500 ns ( 47.79 % ) " "Info: Total cell delay = 6.500 ns ( 47.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 52.21 % ) " "Info: Total interconnect delay = 7.100 ns ( 52.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WREN source 13.600 ns - Longest register " "Info: - Longest clock path from clock \"WREN\" to source register is 13.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns WREN 1 CLK PIN_8 9 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 9; CLK Node = 'WREN'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WREN } "NODE_NAME" } } { "Mif1.bdf" "" { Schematic "C:/cunchuqi/Mif1.bdf" { { 168 -264 -96 184 "WREN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.600 ns) 10.800 ns CNT10B:inst1\|CLKOUT~3 2 COMB LC1_F9 177 " "Info: 2: + IC(4.300 ns) + CELL(1.600 ns) = 10.800 ns; Loc. = LC1_F9; Fanout = 177; COMB Node = 'CNT10B:inst1\|CLKOUT~3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { WREN CNT10B:inst1|CLKOUT~3 } "NODE_NAME" } } { "CNT10B.vhd" "" { Text "C:/cunchuqi/CNT10B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 13.600 ns CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 3 REG LC5_D16 19 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 13.600 ns; Loc. = LC5_D16; Fanout = 19; REG Node = 'CNT10B:inst1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.500 ns ( 47.79 % ) " "Info: Total cell delay = 6.500 ns ( 47.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 52.21 % ) " "Info: Total interconnect delay = 7.100 ns ( 52.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.200 ns + " "Info: + Micro setup delay of destination is 1.200 ns" {  } { { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.300 ns" { CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 1.500ns } { 0.000ns 0.800ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.600 ns" { WREN CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.600 ns" { WREN WREN~out CNT10B:inst1|CLKOUT~3 CNT10B:inst1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 4.300ns 2.800ns } { 0.000ns 4.900ns 1.600ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6]~reg_ra0 } {  } {  } "" } } { "altram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}