mif1.hier_info

存储示波器

|Mif1
ADDA <= ADCINT:inst.ADDA
CLK => ADCINT:inst.CLK
CLK => CNT10B:inst1.CLK
EOC => ADCINT:inst.EOC
D[0] => ADCINT:inst.D[0]
D[1] => ADCINT:inst.D[1]
D[2] => ADCINT:inst.D[2]
D[3] => ADCINT:inst.D[3]
D[4] => ADCINT:inst.D[4]
D[5] => ADCINT:inst.D[5]
D[6] => ADCINT:inst.D[6]
D[7] => ADCINT:inst.D[7]
OE <= ADCINT:inst.OE
START <= ADCINT:inst.START
ALE <= ADCINT:inst.ALE
Q[0] <= ram8:inst2.q[0]
Q[1] <= ram8:inst2.q[1]
Q[2] <= ram8:inst2.q[2]
Q[3] <= ram8:inst2.q[3]
Q[4] <= ram8:inst2.q[4]
Q[5] <= ram8:inst2.q[5]
Q[6] <= ram8:inst2.q[6]
Q[7] <= ram8:inst2.q[7]
CLR => CNT10B:inst1.CLR
WREN => CNT10B:inst1.WE
WREN => ram8:inst2.we


|Mif1|ADCINT:inst
D[0] => REGL[0].DATAIN
D[1] => REGL[1].DATAIN
D[2] => REGL[2].DATAIN
D[3] => REGL[3].DATAIN
D[4] => REGL[4].DATAIN
D[5] => REGL[5].DATAIN
D[6] => REGL[6].DATAIN
D[7] => REGL[7].DATAIN
CLK => current_state~0.IN1
EOC => next_state.st3.DATAB
EOC => Selector0.IN2
ALE <= current_state.st1.DB_MAX_OUTPUT_PORT_TYPE
START <= current_state.st1.DB_MAX_OUTPUT_PORT_TYPE
OE <= OE~0.DB_MAX_OUTPUT_PORT_TYPE
ADDA <= <VCC>
LOCK0 <= current_state.st4.DB_MAX_OUTPUT_PORT_TYPE
Q[0] <= REGL[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= REGL[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= REGL[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= REGL[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= REGL[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= REGL[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= REGL[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= REGL[7].DB_MAX_OUTPUT_PORT_TYPE


|Mif1|ram8:inst2
address[0] => lpm_ram_dq:lpm_ram_dq_component.address[0]
address[1] => lpm_ram_dq:lpm_ram_dq_component.address[1]
address[2] => lpm_ram_dq:lpm_ram_dq_component.address[2]
address[3] => lpm_ram_dq:lpm_ram_dq_component.address[3]
address[4] => lpm_ram_dq:lpm_ram_dq_component.address[4]
address[5] => lpm_ram_dq:lpm_ram_dq_component.address[5]
address[6] => lpm_ram_dq:lpm_ram_dq_component.address[6]
address[7] => lpm_ram_dq:lpm_ram_dq_component.address[7]
address[8] => lpm_ram_dq:lpm_ram_dq_component.address[8]
data[0] => lpm_ram_dq:lpm_ram_dq_component.data[0]
data[1] => lpm_ram_dq:lpm_ram_dq_component.data[1]
data[2] => lpm_ram_dq:lpm_ram_dq_component.data[2]
data[3] => lpm_ram_dq:lpm_ram_dq_component.data[3]
data[4] => lpm_ram_dq:lpm_ram_dq_component.data[4]
data[5] => lpm_ram_dq:lpm_ram_dq_component.data[5]
data[6] => lpm_ram_dq:lpm_ram_dq_component.data[6]
data[7] => lpm_ram_dq:lpm_ram_dq_component.data[7]
inclock => lpm_ram_dq:lpm_ram_dq_component.inclock
we => lpm_ram_dq:lpm_ram_dq_component.we
q[0] <= lpm_ram_dq:lpm_ram_dq_component.q[0]
q[1] <= lpm_ram_dq:lpm_ram_dq_component.q[1]
q[2] <= lpm_ram_dq:lpm_ram_dq_component.q[2]
q[3] <= lpm_ram_dq:lpm_ram_dq_component.q[3]
q[4] <= lpm_ram_dq:lpm_ram_dq_component.q[4]
q[5] <= lpm_ram_dq:lpm_ram_dq_component.q[5]
q[6] <= lpm_ram_dq:lpm_ram_dq_component.q[6]
q[7] <= lpm_ram_dq:lpm_ram_dq_component.q[7]


|Mif1|ram8:inst2|lpm_ram_dq:lpm_ram_dq_component
data[0] => altram:sram.data[0]
data[1] => altram:sram.data[1]
data[2] => altram:sram.data[2]
data[3] => altram:sram.data[3]
data[4] => altram:sram.data[4]
data[5] => altram:sram.data[5]
data[6] => altram:sram.data[6]
data[7] => altram:sram.data[7]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
address[8] => altram:sram.address[8]
inclock => altram:sram.clocki
outclock => ~NO_FANOUT~
we => altram:sram.we
q[0] <= altram:sram.q[0]
q[1] <= altram:sram.q[1]
q[2] <= altram:sram.q[2]
q[3] <= altram:sram.q[3]
q[4] <= altram:sram.q[4]
q[5] <= altram:sram.q[5]
q[6] <= altram:sram.q[6]
q[7] <= altram:sram.q[7]


|Mif1|ram8:inst2|lpm_ram_dq:lpm_ram_dq_component|altram:sram
we => segment[0][7].WE
we => segment[0][6].WE
we => segment[0][5].WE
we => segment[0][4].WE
we => segment[0][3].WE
we => segment[0][2].WE
we => segment[0][1].WE
we => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[0][7].DATAIN
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
address[8] => segment[0][7].WADDR8
address[8] => segment[0][7].RADDR8
address[8] => segment[0][6].WADDR8
address[8] => segment[0][6].RADDR8
address[8] => segment[0][5].WADDR8
address[8] => segment[0][5].RADDR8
address[8] => segment[0][4].WADDR8
address[8] => segment[0][4].RADDR8
address[8] => segment[0][3].WADDR8
address[8] => segment[0][3].RADDR8
address[8] => segment[0][2].WADDR8
address[8] => segment[0][2].RADDR8
address[8] => segment[0][1].WADDR8
address[8] => segment[0][1].RADDR8
address[8] => segment[0][0].WADDR8
address[8] => segment[0][0].RADDR8
clocki => segment[0][7].CLK0
clocki => segment[0][6].CLK0
clocki => segment[0][5].CLK0
clocki => segment[0][4].CLK0
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => ~NO_FANOUT~
be => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT


|Mif1|CNT10B:inst1
LOCK0 => CLK0~0.DATAB
CLR => CQI[8].ACLR
CLR => CQI[7].ACLR
CLR => CQI[6].ACLR
CLR => CQI[5].ACLR
CLR => CQI[4].ACLR
CLR => CQI[3].ACLR
CLR => CQI[2].ACLR
CLR => CQI[1].ACLR
CLR => CQI[0].ACLR
CLK => CLK0~0.DATAA
WE => CLK0~0.OUTPUTSELECT
DOUT[0] <= CQI[0].DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= CQI[3].DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= CQI[4].DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= CQI[5].DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= CQI[6].DB_MAX_OUTPUT_PORT_TYPE
DOUT[7] <= CQI[7].DB_MAX_OUTPUT_PORT_TYPE
DOUT[8] <= CQI[8].DB_MAX_OUTPUT_PORT_TYPE
CLKOUT <= CLK0~0.DB_MAX_OUTPUT_PORT_TYPE