dds_vhdl.map.rpt
来自「dds数字移相信号发生器,功能齐全通过验证」· RPT 代码 · 共 306 行 · 第 1/5 页
RPT
306 行
; |decode_ogi:auto_generated| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated ; work ;
; |lpm_shiftreg:jtag_ir_register| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register ; work ;
; |sld_dffex:BROADCAST| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:BROADCAST ; work ;
; |sld_dffex:IRF_ENA_0| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 ; work ;
; |sld_dffex:IRF_ENA| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA ; work ;
; |sld_dffex:IRSR| ; 11 (11) ; 9 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 9 (9) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:IRSR ; work ;
; |sld_dffex:RESET| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:RESET ; work ;
; |sld_dffex:\GEN_IRF:1:IRF| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF ; work ;
; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ; work ;
; |sld_jtag_state_machine:jtag_state_machine| ; 21 (21) ; 19 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 19 (19) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ; work ;
; |sld_rom_sr:HUB_INFO_REG| ; 21 (21) ; 9 ; 0 ; 0 ; 0 ; 12 (12) ; 0 (0) ; 9 (9) ; 5 (5) ; 0 (0) ; |DDS_VHDL|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ; work ;
; |sld_signaltap:DDS_VHDL| ; 497 (0) ; 407 ; 36864 ; 0 ; 0 ; 90 (0) ; 251 (0) ; 156 (0) ; 48 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL ; work ;
; |sld_signaltap_impl:sld_signaltap_body| ; 497 (80) ; 407 ; 36864 ; 0 ; 0 ; 90 (4) ; 251 (74) ; 156 (2) ; 48 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body ; work ;
; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 0 (0) ; 0 ; 36864 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; work ;
; |altsyncram_imi2:auto_generated| ; 0 (0) ; 0 ; 36864 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated ; work ;
; |sld_acquisition_buffer:sld_acquisition_buffer_inst| ; 24 (3) ; 21 ; 0 ; 0 ; 0 ; 3 (2) ; 10 (0) ; 11 (1) ; 11 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst ; work ;
; |lpm_counter:\write_address_non_zero_gen:write_pointer_counter| ; 11 (0) ; 10 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 10 (0) ; 11 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter ; work ;
; |cntr_hek:auto_generated| ; 11 (11) ; 10 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 10 (10) ; 11 (11) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated ; work ;
; |lpm_ff:\gen_non_zero_sample_depth:trigger_address_register| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_ff:\gen_non_zero_sample_depth:trigger_address_register ; work ;
; |sld_ela_control:ela_control| ; 296 (6) ; 229 ; 0 ; 0 ; 0 ; 67 (5) ; 167 (1) ; 62 (0) ; 20 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control ; work ;
; |lpm_shiftreg:trigger_config_deserialize| ; 19 (19) ; 19 ; 0 ; 0 ; 0 ; 0 (0) ; 19 (19) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; work ;
; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 216 (0) ; 180 ; 0 ; 0 ; 0 ; 36 (0) ; 144 (0) ; 36 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; work ;
; |lpm_shiftreg:trigger_condition_deserialize| ; 108 (108) ; 108 ; 0 ; 0 ; 0 ; 0 (0) ; 108 (108) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; work ;
; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 108 (0) ; 72 ; 0 ; 0 ; 0 ; 36 (0) ; 36 (0) ; 36 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDS_VHDL|sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_l⌨️ 快捷键说明
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