dds_vhdl.tan.rpt

来自「dds数字移相信号发生器,功能齐全通过验证」· RPT 代码 · 共 179 行 · 第 1/5 页

; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK                          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                            ; To                                                                                                                                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0   ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg0  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg1  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg2  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg3  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg4  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg5  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg6  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg7  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg8  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_address_reg9  ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;
; N/A                                     ; 144.09 MHz ( period = 6.940 ns )                    ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg1   ; CLK        ; CLK      ; None                        ; None                      ; 6.622 ns                ;