dds_vhdl.tan.rpt

来自「dds数字移相信号发生器,功能齐全通过验证」· RPT 代码 · 共 179 行 · 第 1/5 页

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                                                            ; To                                                                                                                                                                                                                                   ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 3.048 ns                         ; FWORD[1]                                                                                                                                                                                                        ; REG32B:u2|DOUT[31]                                                                                                                                                                                                                   ; --                           ; CLK                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 14.384 ns                        ; sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8]                                                                                                                                ; POUT[8]                                                                                                                                                                                                                              ; CLK                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                        ; altera_reserved_tdo                                                                                                                                                                                                                  ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.815 ns                         ; altera_internal_jtag                                                                                                                                                                                            ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[107] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 135.32 MHz ( period = 7.390 ns ) ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]                                                                                                                                                                   ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                                                                                                                     ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 144.09 MHz ( period = 6.940 ns ) ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] ; sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg3                                                           ; CLK                          ; CLK                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                                                                 ;                                                                                                                                                                                                                                      ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;