dds_vhdl.tan.rpt

来自「dds数字移相信号发生器,功能齐全通过验证」· RPT 代码 · 共 179 行 · 第 1/5 页

Classic Timing Analyzer report for DDS_VHDL
Wed Sep 10 11:58:59 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. Clock Setup: 'altera_internal_jtag~TCKUTAP'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
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Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by