reg10b.vhd

来自「dds数字移相信号发生器,功能齐全通过验证」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
    PORT (  Load : IN STD_LOGIC;
             DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
            DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );
END REG10B;
ARCHITECTURE behav OF REG10B IS
BEGIN
    PROCESS(Load, DIN)
   BEGIN
   IF Load'EVENT AND Load = '1' THEN   DOUT <= DIN;   END IF;
    END PROCESS;
END behav;