dds_vhdl.tan.qmsg

来自「dds数字移相信号发生器,功能齐全通过验证」· QMSG 代码 · 共 9 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "REG32B:u2\|DOUT\[31\] FWORD\[1\] CLK 3.048 ns register " "Info: tsu for register \"REG32B:u2\|DOUT\[31\]\" (data pin = \"FWORD\[1\]\", clock pin = \"CLK\") is 3.048 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.774 ns + Longest pin register " "Info: + Longest pin to register delay is 10.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns FWORD\[1\] 1 PIN PIN_234 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_234; Fanout = 4; PIN Node = 'FWORD\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FWORD[1] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.251 ns) + CELL(0.575 ns) 9.301 ns REG32B:u2\|DOUT\[21\]~59COUT1 2 COMB LC_X16_Y18_N5 2 " "Info: 2: + IC(7.251 ns) + CELL(0.575 ns) = 9.301 ns; Loc. = LC_X16_Y18_N5; Fanout = 2; COMB Node = 'REG32B:u2\|DOUT\[21\]~59COUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.826 ns" { FWORD[1] REG32B:u2|DOUT[21]~59COUT1 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 9.381 ns REG32B:u2\|DOUT\[22\]~49COUT1 3 COMB LC_X16_Y18_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 9.381 ns; Loc. = LC_X16_Y18_N6; Fanout = 2; COMB Node = 'REG32B:u2\|DOUT\[22\]~49COUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { REG32B:u2|DOUT[21]~59COUT1 REG32B:u2|DOUT[22]~49COUT1 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 9.461 ns REG32B:u2\|DOUT\[23\]~50COUT1 4 COMB LC_X16_Y18_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 9.461 ns; Loc. = LC_X16_Y18_N7; Fanout = 2; COMB Node = 'REG32B:u2\|DOUT\[23\]~50COUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { REG32B:u2|DOUT[22]~49COUT1 REG32B:u2|DOUT[23]~50COUT1 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 9.541 ns REG32B:u2\|DOUT\[24\]~51COUT1 5 COMB LC_X16_Y18_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 9.541 ns; Loc. = LC_X16_Y18_N8; Fanout = 2; COMB Node = 'REG32B:u2\|DOUT\[24\]~51COUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { REG32B:u2|DOUT[23]~50COUT1 REG32B:u2|DOUT[24]~51COUT1 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 9.799 ns REG32B:u2\|DOUT\[25\]~52 6 COMB LC_X16_Y18_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 9.799 ns; Loc. = LC_X16_Y18_N9; Fanout = 6; COMB Node = 'REG32B:u2\|DOUT\[25\]~52'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { REG32B:u2|DOUT[24]~51COUT1 REG32B:u2|DOUT[25]~52 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 9.935 ns REG32B:u2\|DOUT\[30\]~57 7 COMB LC_X16_Y17_N4 1 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 9.935 ns; Loc. = LC_X16_Y17_N4; Fanout = 1; COMB Node = 'REG32B:u2\|DOUT\[30\]~57'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { REG32B:u2|DOUT[25]~52 REG32B:u2|DOUT[30]~57 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 10.774 ns REG32B:u2\|DOUT\[31\] 8 REG LC_X16_Y17_N5 5 " "Info: 8: + IC(0.000 ns) + CELL(0.839 ns) = 10.774 ns; Loc. = LC_X16_Y17_N5; Fanout = 5; REG Node = 'REG32B:u2\|DOUT\[31\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { REG32B:u2|DOUT[30]~57 REG32B:u2|DOUT[31] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.523 ns ( 32.70 % ) " "Info: Total cell delay = 3.523 ns ( 32.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.251 ns ( 67.30 % ) " "Info: Total interconnect delay = 7.251 ns ( 67.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.774 ns" { FWORD[1] REG32B:u2|DOUT[21]~59COUT1 REG32B:u2|DOUT[22]~49COUT1 REG32B:u2|DOUT[23]~50COUT1 REG32B:u2|DOUT[24]~51COUT1 REG32B:u2|DOUT[25]~52 REG32B:u2|DOUT[30]~57 REG32B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.774 ns" { FWORD[1] FWORD[1]~out0 REG32B:u2|DOUT[21]~59COUT1 REG32B:u2|DOUT[22]~49COUT1 REG32B:u2|DOUT[23]~50COUT1 REG32B:u2|DOUT[24]~51COUT1 REG32B:u2|DOUT[25]~52 REG32B:u2|DOUT[30]~57 REG32B:u2|DOUT[31] } { 0.000ns 0.000ns 7.251ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.763 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 7.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_179 462 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_179; Fanout = 462; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.583 ns) + CELL(0.711 ns) 7.763 ns REG32B:u2\|DOUT\[31\] 2 REG LC_X16_Y17_N5 5 " "Info: 2: + IC(5.583 ns) + CELL(0.711 ns) = 7.763 ns; Loc. = LC_X16_Y17_N5; Fanout = 5; REG Node = 'REG32B:u2\|DOUT\[31\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.294 ns" { CLK REG32B:u2|DOUT[31] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "C:/dds数字移相信号发生器/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.08 % ) " "Info: Total cell delay = 2.180 ns ( 28.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.583 ns ( 71.92 % ) " "Info: Total interconnect delay = 5.583 ns ( 71.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.763 ns" { CLK REG32B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.763 ns" { CLK CLK~out0 REG32B:u2|DOUT[31] } { 0.000ns 0.000ns 5.583ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.774 ns" { FWORD[1] REG32B:u2|DOUT[21]~59COUT1 REG32B:u2|DOUT[22]~49COUT1 REG32B:u2|DOUT[23]~50COUT1 REG32B:u2|DOUT[24]~51COUT1 REG32B:u2|DOUT[25]~52 REG32B:u2|DOUT[30]~57 REG32B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.774 ns" { FWORD[1] FWORD[1]~out0 REG32B:u2|DOUT[21]~59COUT1 REG32B:u2|DOUT[22]~49COUT1 REG32B:u2|DOUT[23]~50COUT1 REG32B:u2|DOUT[24]~51COUT1 REG32B:u2|DOUT[25]~52 REG32B:u2|DOUT[30]~57 REG32B:u2|DOUT[31] } { 0.000ns 0.000ns 7.251ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.763 ns" { CLK REG32B:u2|DOUT[31] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.763 ns" { CLK CLK~out0 REG32B:u2|DOUT[31] } { 0.000ns 0.000ns 5.583ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK POUT\[8\] sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[8\] 14.384 ns memory " "Info: tco from clock \"CLK\" to destination pin \"POUT\[8\]\" through memory \"sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[8\]\" is 14.384 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.769 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 7.769 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_179 462 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_179; Fanout = 462; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.592 ns) + CELL(0.708 ns) 7.769 ns sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[8\] 2 MEM M4K_X17_Y17 2 " "Info: 2: + IC(5.592 ns) + CELL(0.708 ns) = 7.769 ns; Loc. = M4K_X17_Y17; Fanout = 2; MEM Node = 'sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[8\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { CLK sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/dds数字移相信号发生器/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 28.02 % ) " "Info: Total cell delay = 2.177 ns ( 28.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.592 ns ( 71.98 % ) " "Info: Total interconnect delay = 5.592 ns ( 71.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.769 ns" { CLK sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.769 ns" { CLK CLK~out0 sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] } { 0.000ns 0.000ns 5.592ns } { 0.000ns 1.469ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/dds数字移相信号发生器/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.965 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[8\] 1 MEM M4K_X17_Y17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X17_Y17; Fanout = 2; MEM Node = 'sin_rom:u6\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\|q_a\[8\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] } "NODE_NAME" } } { "db/altsyncram_u631.tdf" "" { Text "C:/dds数字移相信号发生器/db/altsyncram_u631.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.753 ns) + CELL(2.108 ns) 5.965 ns POUT\[8\] 2 PIN PIN_85 0 " "Info: 2: + IC(3.753 ns) + CELL(2.108 ns) = 5.965 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'POUT\[8\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.861 ns" { sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] POUT[8] } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns ( 37.08 % ) " "Info: Total cell delay = 2.212 ns ( 37.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.753 ns ( 62.92 % ) " "Info: Total interconnect delay = 3.753 ns ( 62.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.965 ns" { sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] POUT[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.965 ns" { sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] POUT[8] } { 0.000ns 3.753ns } { 0.104ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.769 ns" { CLK sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.769 ns" { CLK CLK~out0 sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] } { 0.000ns 0.000ns 5.592ns } { 0.000ns 1.469ns 0.708ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.965 ns" { sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] POUT[8] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.965 ns" { sin_rom:u6|altsyncram:altsyncram_component|altsyncram_u631:auto_generated|q_a[8] POUT[8] } { 0.000ns 3.753ns } { 0.104ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}