dds_vhdl.tan.qmsg

来自「dds数字移相信号发生器,功能齐全通过验证」· QMSG 代码 · 共 9 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|safe_q\[1\] memory sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_imi2:auto_generated\|ram_block1a8~porta_datain_reg0 144.09 MHz 6.94 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 144.09 MHz between source register \"sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|safe_q\[1\]\" and destination memory \"sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_imi2:auto_generated\|ram_block1a8~porta_datain_reg0\" (period= 6.94 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.622 ns + Longest register memory " "Info: + Longest register to memory delay is 6.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|safe_q\[1\] 1 REG LC_X16_Y10_N6 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y10_N6; Fanout = 14; REG Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|safe_q\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella1~COUTCOUT1 2 COMB LC_X16_Y10_N6 2 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X16_Y10_N6; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella1~COUTCOUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.098 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.178 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella2~COUTCOUT1 3 COMB LC_X16_Y10_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X16_Y10_N7; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella2~COUTCOUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 49 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella3~COUTCOUT1 4 COMB LC_X16_Y10_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X16_Y10_N8; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella3~COUTCOUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 57 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.516 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella4~COUT 5 COMB LC_X16_Y10_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.516 ns; Loc. = LC_X16_Y10_N9; Fanout = 6; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella4~COUT'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 65 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.652 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella9~COUT 6 COMB LC_X16_Y9_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.652 ns; Loc. = LC_X16_Y9_N4; Fanout = 1; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella9~COUT'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 105 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.273 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|cout 7 COMB LC_X16_Y9_N5 4 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.273 ns; Loc. = LC_X16_Y9_N5; Fanout = 4; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|cout'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 152 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.287 ns) + CELL(0.114 ns) 3.674 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~109 8 COMB LC_X16_Y10_N0 2 " "Info: 8: + IC(1.287 ns) + CELL(0.114 ns) = 3.674 ns; Loc. = LC_X16_Y10_N0; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~109'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.401 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 } "NODE_NAME" } } { "../altera/71/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_ela_control.vhd" 1211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.970 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|buffer_write_ena_int~43 9 COMB LC_X16_Y10_N1 126 " "Info: 9: + IC(0.182 ns) + CELL(0.114 ns) = 3.970 ns; Loc. = LC_X16_Y10_N1; Fanout = 126; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|buffer_write_ena_int~43'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.687 ns) + CELL(0.965 ns) 6.622 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_imi2:auto_generated\|ram_block1a8~porta_datain_reg0 10 MEM M4K_X17_Y6 1 " "Info: 10: + IC(1.687 ns) + CELL(0.965 ns) = 6.622 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_imi2:auto_generated\|ram_block1a8~porta_datain_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.652 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_imi2.tdf" "" { Text "C:/dds数字移相信号发生器/db/altsyncram_imi2.tdf" 288 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.943 ns ( 44.44 % ) " "Info: Total cell delay = 2.943 ns ( 44.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.679 ns ( 55.56 % ) " "Info: Total interconnect delay = 3.679 ns ( 55.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.622 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.622 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.287ns 0.182ns 1.687ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.114ns 0.114ns 0.965ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.732 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 7.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_179 462 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_179; Fanout = 462; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.541 ns) + CELL(0.722 ns) 7.732 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_imi2:auto_generated\|ram_block1a8~porta_datain_reg0 2 MEM M4K_X17_Y6 1 " "Info: 2: + IC(5.541 ns) + CELL(0.722 ns) = 7.732 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_imi2:auto_generated\|ram_block1a8~porta_datain_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.263 ns" { CLK sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_imi2.tdf" "" { Text "C:/dds数字移相信号发生器/db/altsyncram_imi2.tdf" 288 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 28.34 % ) " "Info: Total cell delay = 2.191 ns ( 28.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.541 ns ( 71.66 % ) " "Info: Total interconnect delay = 5.541 ns ( 71.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.732 ns" { CLK sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.732 ns" { CLK CLK~out0 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } { 0.000ns 0.000ns 5.541ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.733 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_179 462 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_179; Fanout = 462; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS_VHDL.vhd" "" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.553 ns) + CELL(0.711 ns) 7.733 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|safe_q\[1\] 2 REG LC_X16_Y10_N6 14 " "Info: 2: + IC(5.553 ns) + CELL(0.711 ns) = 7.733 ns; Loc. = LC_X16_Y10_N6; Fanout = 14; REG Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|safe_q\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.264 ns" { CLK sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.19 % ) " "Info: Total cell delay = 2.180 ns ( 28.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.553 ns ( 71.81 % ) " "Info: Total interconnect delay = 5.553 ns ( 71.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.733 ns" { CLK sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.733 ns" { CLK CLK~out0 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] } { 0.000ns 0.000ns 5.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.732 ns" { CLK sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.732 ns" { CLK CLK~out0 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } { 0.000ns 0.000ns 5.541ns } { 0.000ns 1.469ns 0.722ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.733 ns" { CLK sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.733 ns" { CLK CLK~out0 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] } { 0.000ns 0.000ns 5.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 123 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_imi2.tdf" "" { Text "C:/dds数字移相信号发生器/db/altsyncram_imi2.tdf" 288 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.622 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.622 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.287ns 0.182ns 1.687ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.114ns 0.114ns 0.965ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.732 ns" { CLK sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.732 ns" { CLK CLK~out0 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } { 0.000ns 0.000ns 5.541ns } { 0.000ns 1.469ns 0.722ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.733 ns" { CLK sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.733 ns" { CLK CLK~out0 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[1] } { 0.000ns 0.000ns 5.553ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 135.32 MHz 7.39 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 135.32 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 7.39 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.404 ns + Longest register register " "Info: + Longest register to register delay is 3.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 1 REG LC_X22_Y10_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y10_N6; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.442 ns) 1.580 ns sld_hub:sld_hub_inst\|hub_tdo_reg~619 2 COMB LC_X20_Y10_N9 1 " "Info: 2: + IC(1.138 ns) + CELL(0.442 ns) = 1.580 ns; Loc. = LC_X20_Y10_N9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~619'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.580 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] sld_hub:sld_hub_inst|hub_tdo_reg~619 } "NODE_NAME" } } { "../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.217 ns) + CELL(0.607 ns) 3.404 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LC_X21_Y9_N3 1 " "Info: 3: + IC(1.217 ns) + CELL(0.607 ns) = 3.404 ns; Loc. = LC_X21_Y9_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~619 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.049 ns ( 30.82 % ) " "Info: Total cell delay = 1.049 ns ( 30.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.355 ns ( 69.18 % ) " "Info: Total interconnect delay = 2.355 ns ( 69.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.404 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] sld_hub:sld_hub_inst|hub_tdo_reg~619 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.404 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] sld_hub:sld_hub_inst|hub_tdo_reg~619 sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 1.138ns 1.217ns } { 0.000ns 0.442ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.030 ns - Smallest " "Info: - Smallest clock skew is -0.030 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.280 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.280 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 372 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 372; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.569 ns) + CELL(0.711 ns) 5.280 ns sld_hub:sld_hub_inst\|hub_tdo_reg 2 REG LC_X21_Y9_N3 1 " "Info: 2: + IC(4.569 ns) + CELL(0.711 ns) = 5.280 ns; Loc. = LC_X21_Y9_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.47 % ) " "Info: Total cell delay = 0.711 ns ( 13.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.569 ns ( 86.53 % ) " "Info: Total interconnect delay = 4.569 ns ( 86.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 4.569ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.310 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 372 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 372; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.599 ns) + CELL(0.711 ns) 5.310 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 2 REG LC_X22_Y10_N6 3 " "Info: 2: + IC(4.599 ns) + CELL(0.711 ns) = 5.310 ns; Loc. = LC_X22_Y10_N6; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.39 % ) " "Info: Total cell delay = 0.711 ns ( 13.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.599 ns ( 86.61 % ) " "Info: Total interconnect delay = 4.599 ns ( 86.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.599ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 4.569ns } { 0.000ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.599ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.404 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] sld_hub:sld_hub_inst|hub_tdo_reg~619 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.404 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] sld_hub:sld_hub_inst|hub_tdo_reg~619 sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 1.138ns 1.217ns } { 0.000ns 0.442ns 0.607ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.280 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 4.569ns } { 0.000ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.310 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.599ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}