dds_vhdl.fit.qmsg

来自「dds数字移相信号发生器,功能齐全通过验证」· QMSG 代码 · 共 51 行 · 第 1/3 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.707 ns register memory " "Info: Estimated most critical path is register to memory delay of 6.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|safe_q\[0\] 1 REG LAB_X16_Y10 41 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y10; Fanout = 41; REG Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|safe_q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[0] } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.575 ns) 1.035 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella0~COUTCOUT1 2 COMB LAB_X16_Y10 2 " "Info: 2: + IC(0.460 ns) + CELL(0.575 ns) = 1.035 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella0~COUTCOUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.035 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[0] sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella0~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.115 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella1~COUTCOUT1 3 COMB LAB_X16_Y10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.115 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella1~COUTCOUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella0~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.195 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella2~COUTCOUT1 4 COMB LAB_X16_Y10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.195 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella2~COUTCOUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 49 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.275 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella3~COUTCOUT1 5 COMB LAB_X16_Y10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.275 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella3~COUTCOUT1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 57 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.533 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella4~COUT 6 COMB LAB_X16_Y10 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.533 ns; Loc. = LAB_X16_Y10; Fanout = 6; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella4~COUT'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 65 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.669 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella9~COUT 7 COMB LAB_X16_Y9 1 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.669 ns; Loc. = LAB_X16_Y9; Fanout = 1; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|counter_cella9~COUT'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 105 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.348 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|cout 8 COMB LAB_X16_Y9 4 " "Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 2.348 ns; Loc. = LAB_X16_Y9; Fanout = 4; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_hek:auto_generated\|cout'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout } "NODE_NAME" } } { "db/cntr_hek.tdf" "" { Text "C:/dds数字移相信号发生器/db/cntr_hek.tdf" 152 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.932 ns) + CELL(0.442 ns) 3.722 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~109 9 COMB LAB_X16_Y10 2 " "Info: 9: + IC(0.932 ns) + CELL(0.442 ns) = 3.722 ns; Loc. = LAB_X16_Y10; Fanout = 2; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~109'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.374 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 } "NODE_NAME" } } { "../altera/71/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_ela_control.vhd" 1211 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.063 ns) + CELL(0.590 ns) 4.375 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|buffer_write_ena_int~43 10 COMB LAB_X16_Y10 396 " "Info: 10: + IC(0.063 ns) + CELL(0.590 ns) = 4.375 ns; Loc. = LAB_X16_Y10; Fanout = 396; COMB Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|buffer_write_ena_int~43'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.367 ns) + CELL(0.965 ns) 6.707 ns sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_imi2:auto_generated\|ram_block1a8~porta_datain_reg0 11 MEM M4K_X17_Y6 1 " "Info: 11: + IC(1.367 ns) + CELL(0.965 ns) = 6.707 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'sld_signaltap:DDS_VHDL\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_imi2:auto_generated\|ram_block1a8~porta_datain_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.332 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_imi2.tdf" "" { Text "C:/dds数字移相信号发生器/db/altsyncram_imi2.tdf" 288 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.885 ns ( 57.92 % ) " "Info: Total cell delay = 3.885 ns ( 57.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.822 ns ( 42.08 % ) " "Info: Total interconnect delay = 2.822 ns ( 42.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|safe_q[0] sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella0~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella1~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella2~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella3~COUTCOUT1 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella4~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|counter_cella9~COUT sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hek:auto_generated|cout sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~109 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:DDS_VHDL|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_imi2:auto_generated|ram_block1a8~porta_datain_reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 10 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 10%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X12_Y0 X23_Y10 " "Info: The peak interconnect region extends from location X12_Y0 to location X23_Y10" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/dds数字移相信号发生器/DDS_VHDL.fit.smsg " "Info: Generated suppressed messages file C:/dds数字移相信号发生器/DDS_VHDL.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "184 " "Info: Allocated 184 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 10 11:58:51 2008 " "Info: Processing ended: Wed Sep 10 11:58:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}