dds_vhdl.hif

dds数字移相信号发生器,功能齐全通过验证

}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
18
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
1
PARAMETER_SIGNED_DEC
USR
enable_clk_edge_def
0
PARAMETER_SIGNED_DEC
USR
enable_async_glitch
0
PARAMETER_SIGNED_DEC
USR
enable_sync_normal
1
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
10
PARAMETER_SIGNED_DEC
USR
sample_depth
1024
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
73
PARAMETER_SIGNED_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(acq_trigger_in)
17 downto 0
PARAMETER_STRING
USR
 constraint(status)
3 downto 0
PARAMETER_STRING
USR
}
# lmf
..|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|DDS_VHDL.(11).cnf
db|DDS_VHDL.(11).cnf
# case_insensitive
# source_file
..|altera|71|quartus|libraries|megafunctions|lpm_shiftreg.tdf
3afc744803f77b6fa5676c390d0fb8f
6
# user_parameter {
LPM_WIDTH
19
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
load
-1
1
data9
-1
1
data8
-1
1
data7
-1
1
data6
-1
1
data5
-1
1
data4
-1
1
data3
-1
1
data2
-1
1
data18
-1
1
data17
-1
1
data16
-1
1
data15
-1
1
data14
-1
1
data13
-1
1
data12
-1
1
data11
-1
1
data10
-1
1
data1
-1
1
data0
-1
1
}
# include_file {
..|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
..|altera|71|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|altera|71|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
}
# lmf
..|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|DDS_VHDL.(12).cnf
db|DDS_VHDL.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|altera|71|quartus|libraries|megafunctions|sld_ela_control.vhd
c344b9ef4eed6f1fb9dd17ea42ba423
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
18
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
73
PARAMETER_SIGNED_DEC
USR
inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
17 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_ena)
0 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
..|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
lpm_shiftreg
# storage
db|DDS_VHDL.(13).cnf
db|DDS_VHDL.(13).cnf
# case_insensitive
# source_file
..|altera|71|quartus|libraries|megafunctions|lpm_shiftreg.tdf
3afc744803f77b6fa5676c390d0fb8f
6
# user_parameter {
LPM_WIDTH
54
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q53
-1
3
q52
-1
3
q51
-1
3
q50
-1
3
q5
-1
3
q49
-1
3
q48
-1
3
q47
-1
3
q46
-1
3
q45
-1
3
q44
-1
3
q43
-1
3
q42
-1
3
q41
-1
3
q40
-1
3
q4
-1
3
q39
-1
3
q38
-1
3
q37
-1
3
q36
-1
3
q35
-1
3
q34
-1
3
q33
-1
3
q32
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
load
-1
1
data9
-1
1
data8
-1
1
data7
-1
1
data6
-1
1
data53
-1
1
data52
-1
1
data51
-1
1
data50
-1
1
data5
-1
1
data49
-1
1
data48
-1
1
data47
-1
1
data46
-1
1
data45
-1
1
data44
-1
1
data43
-1
1
data42
-1
1
data41
-1
1
data40
-1
1
data4
-1
1
data39
-1
1
data38
-1
1
data37
-1
1
data36
-1
1
data35
-1
1
data34
-1
1
data33
-1
1
data32
-1
1
data31
-1
1
data30
-1
1
data3
-1
1
data29
-1
1
data28
-1
1
data27
-1
1
data26
-1
1
data25
-1
1
data24
-1
1
data23
-1
1
data22
-1
1
data21
-1
1
data20
-1
1
data2
-1
1
data19
-1
1
data18
-1
1
data17
-1
1
data16
-1
1
data15
-1
1
data14
-1
1
data13
-1
1
data12
-1
1
data11
-1
1
data10
-1
1
data1
-1
1
data0
-1
1
}
# include_file {
..|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
..|altera|71|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|altera|71|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
}
# lmf
..|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|DDS_VHDL.(14).cnf
db|DDS_VHDL.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|altera|71|quartus|libraries|megafunctions|sld_mbpmg.vhd
9c6644fb15e83ca87c1ec811ac7fc2f
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
18
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
17 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
53 downto 0
PARAMETER_STRING
USR
}
# lmf
..|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_sbpmg
# storage
db|DDS_VHDL.(15).cnf
db|DDS_VHDL.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|altera|71|quartus|libraries|megafunctions|sld_mbpmg.vhd
9c6644fb15e83ca87c1ec811ac7fc2f
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
}
# lmf
..|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|DDS_VHDL.(16).cnf
db|DDS_VHDL.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|altera|71|quartus|libraries|megafunctions|sld_mbpmg.vhd
9c6644fb15e83ca87c1ec811ac7fc2f
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
1
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
DEF
 constraint(data_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
2 downto 0
PARAMETER_STRING
USR
}
# lmf
..|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_ela_level_seq_mgr
# storage
db|DDS_VHDL.(17).cnf
db|DDS_VHDL.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|altera|71|quartus|libraries|megafunctions|sld_ela_control.vhd
c344b9ef4eed6f1fb9dd17ea42ba423
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
5
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
2
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
10
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
1
PARAMETER_SIGNED_DEC
USR
 constraint(trigger_level_matched)
1 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_enabled)
1 downto 0
PARAMETER_STRING
USR
 constraint(trigger_ena)
1 downto 0
PARAMETER_STRING
USR
 constraint(enable_trigger)
1 downto 0
PARAMETER_STRING
USR
}
# lmf
..|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_ela_state_machine
# storage
db|DDS_VHDL.(18).cnf
db|DDS_VHDL.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|altera|71|quartus|libraries|megafunctions|sld_ela_control.vhd
c344b9ef4eed6f1fb9dd17ea42ba423
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT