prev_cmp_dds_vhdl.qmsg

dds数字移相信号发生器,功能齐全通过验证

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG32B REG32B:u2 " "Info: Elaborating entity \"REG32B\" for hierarchy \"REG32B:u2\"" {  } { { "DDS_VHDL.vhd" "u2" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 48 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin_rom sin_rom:u3 " "Info: Elaborating entity \"sin_rom\" for hierarchy \"sin_rom:u3\"" {  } { { "DDS_VHDL.vhd" "u3" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 49 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/71/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../altera/71/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram sin_rom:u3\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"sin_rom:u3\|altsyncram:altsyncram_component\"" {  } { { "sin_rom.vhd" "altsyncram_component" { Text "C:/dds数字移相信号发生器/sin_rom.vhd" 83 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "sin_rom:u3\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"sin_rom:u3\|altsyncram:altsyncram_component\"" {  } { { "sin_rom.vhd" "" { Text "C:/dds数字移相信号发生器/sin_rom.vhd" 83 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u631.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_u631.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u631 " "Info: Found entity 1: altsyncram_u631" {  } { { "db/altsyncram_u631.tdf" "" { Text "C:/dds数字移相信号发生器/db/altsyncram_u631.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_u631 sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated " "Info: Elaborating entity \"altsyncram_u631\" for hierarchy \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_u631:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER10B ADDER10B:u4 " "Info: Elaborating entity \"ADDER10B\" for hierarchy \"ADDER10B:u4\"" {  } { { "DDS_VHDL.vhd" "u4" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 50 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG10B REG10B:u5 " "Info: Elaborating entity \"REG10B\" for hierarchy \"REG10B:u5\"" {  } { { "DDS_VHDL.vhd" "u5" { Text "C:/dds数字移相信号发生器/DDS_VHDL.vhd" 51 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_ALLOWING_SIGNAL_TAP_WITH_INCR_SYNTH" "" "Warning: Compiling non-incremental SignalTap II with Incremental Compilation enabled. This will restrict use of other incremental features." {  } {  } 0 0 "Compiling non-incremental SignalTap II with Incremental Compilation enabled. This will restrict use of other incremental features." 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd 5 2 " "Info: Found 5 design units, including 2 entities, in source file ../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 63 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 173 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_signaltap_impl-rtl " "Info: Found design unit 3: sld_signaltap_impl-rtl" {  } { { "../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_signaltap_impl " "Info: Found entity 2: sld_signaltap_impl" {  } { { "../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 353 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}