i8051_all.hier_info

8051的vhdl源代码

|i8051_all
rst => I8051_CTR:U_CTR.rst
rst => I8051_ROM:U_ROM.rst
rst => I8051_RAM:U_RAM.rst
rst => I8051_DEC:U_DEC.rst
rst => I8051_ALU:U_ALU.rst
clk => I8051_CTR:U_CTR.clk
clk => I8051_ROM:U_ROM.clk
clk => I8051_RAM:U_RAM.clk
xrm_addr[0] <= I8051_CTR:U_CTR.xrm_addr[0]
xrm_addr[1] <= I8051_CTR:U_CTR.xrm_addr[1]
xrm_addr[2] <= I8051_CTR:U_CTR.xrm_addr[2]
xrm_addr[3] <= I8051_CTR:U_CTR.xrm_addr[3]
xrm_addr[4] <= I8051_CTR:U_CTR.xrm_addr[4]
xrm_addr[5] <= I8051_CTR:U_CTR.xrm_addr[5]
xrm_addr[6] <= I8051_CTR:U_CTR.xrm_addr[6]
xrm_addr[7] <= I8051_CTR:U_CTR.xrm_addr[7]
xrm_addr[8] <= I8051_CTR:U_CTR.xrm_addr[8]
xrm_addr[9] <= I8051_CTR:U_CTR.xrm_addr[9]
xrm_addr[10] <= I8051_CTR:U_CTR.xrm_addr[10]
xrm_addr[11] <= I8051_CTR:U_CTR.xrm_addr[11]
xrm_addr[12] <= I8051_CTR:U_CTR.xrm_addr[12]
xrm_addr[13] <= I8051_CTR:U_CTR.xrm_addr[13]
xrm_addr[14] <= I8051_CTR:U_CTR.xrm_addr[14]
xrm_addr[15] <= I8051_CTR:U_CTR.xrm_addr[15]
xrm_out_data[0] <= I8051_CTR:U_CTR.xrm_out_data[0]
xrm_out_data[1] <= I8051_CTR:U_CTR.xrm_out_data[1]
xrm_out_data[2] <= I8051_CTR:U_CTR.xrm_out_data[2]
xrm_out_data[3] <= I8051_CTR:U_CTR.xrm_out_data[3]
xrm_out_data[4] <= I8051_CTR:U_CTR.xrm_out_data[4]
xrm_out_data[5] <= I8051_CTR:U_CTR.xrm_out_data[5]
xrm_out_data[6] <= I8051_CTR:U_CTR.xrm_out_data[6]
xrm_out_data[7] <= I8051_CTR:U_CTR.xrm_out_data[7]
xrm_in_data[0] => I8051_CTR:U_CTR.xrm_in_data[0]
xrm_in_data[1] => I8051_CTR:U_CTR.xrm_in_data[1]
xrm_in_data[2] => I8051_CTR:U_CTR.xrm_in_data[2]
xrm_in_data[3] => I8051_CTR:U_CTR.xrm_in_data[3]
xrm_in_data[4] => I8051_CTR:U_CTR.xrm_in_data[4]
xrm_in_data[5] => I8051_CTR:U_CTR.xrm_in_data[5]
xrm_in_data[6] => I8051_CTR:U_CTR.xrm_in_data[6]
xrm_in_data[7] => I8051_CTR:U_CTR.xrm_in_data[7]
xrm_rd <= I8051_CTR:U_CTR.xrm_rd
xrm_wr <= I8051_CTR:U_CTR.xrm_wr
p0_in[0] => I8051_RAM:U_RAM.p0_in[0]
p0_in[1] => I8051_RAM:U_RAM.p0_in[1]
p0_in[2] => I8051_RAM:U_RAM.p0_in[2]
p0_in[3] => I8051_RAM:U_RAM.p0_in[3]
p0_in[4] => I8051_RAM:U_RAM.p0_in[4]
p0_in[5] => I8051_RAM:U_RAM.p0_in[5]
p0_in[6] => I8051_RAM:U_RAM.p0_in[6]
p0_in[7] => I8051_RAM:U_RAM.p0_in[7]
p0_out[0] <= I8051_RAM:U_RAM.p0_out[0]
p0_out[1] <= I8051_RAM:U_RAM.p0_out[1]
p0_out[2] <= I8051_RAM:U_RAM.p0_out[2]
p0_out[3] <= I8051_RAM:U_RAM.p0_out[3]
p0_out[4] <= I8051_RAM:U_RAM.p0_out[4]
p0_out[5] <= I8051_RAM:U_RAM.p0_out[5]
p0_out[6] <= I8051_RAM:U_RAM.p0_out[6]
p0_out[7] <= I8051_RAM:U_RAM.p0_out[7]
p1_in[0] => I8051_RAM:U_RAM.p1_in[0]
p1_in[1] => I8051_RAM:U_RAM.p1_in[1]
p1_in[2] => I8051_RAM:U_RAM.p1_in[2]
p1_in[3] => I8051_RAM:U_RAM.p1_in[3]
p1_in[4] => I8051_RAM:U_RAM.p1_in[4]
p1_in[5] => I8051_RAM:U_RAM.p1_in[5]
p1_in[6] => I8051_RAM:U_RAM.p1_in[6]
p1_in[7] => I8051_RAM:U_RAM.p1_in[7]
p1_out[0] <= I8051_RAM:U_RAM.p1_out[0]
p1_out[1] <= I8051_RAM:U_RAM.p1_out[1]
p1_out[2] <= I8051_RAM:U_RAM.p1_out[2]
p1_out[3] <= I8051_RAM:U_RAM.p1_out[3]
p1_out[4] <= I8051_RAM:U_RAM.p1_out[4]
p1_out[5] <= I8051_RAM:U_RAM.p1_out[5]
p1_out[6] <= I8051_RAM:U_RAM.p1_out[6]
p1_out[7] <= I8051_RAM:U_RAM.p1_out[7]
p2_in[0] => I8051_RAM:U_RAM.p2_in[0]
p2_in[1] => I8051_RAM:U_RAM.p2_in[1]
p2_in[2] => I8051_RAM:U_RAM.p2_in[2]
p2_in[3] => I8051_RAM:U_RAM.p2_in[3]
p2_in[4] => I8051_RAM:U_RAM.p2_in[4]
p2_in[5] => I8051_RAM:U_RAM.p2_in[5]
p2_in[6] => I8051_RAM:U_RAM.p2_in[6]
p2_in[7] => I8051_RAM:U_RAM.p2_in[7]
p2_out[0] <= I8051_RAM:U_RAM.p2_out[0]
p2_out[1] <= I8051_RAM:U_RAM.p2_out[1]
p2_out[2] <= I8051_RAM:U_RAM.p2_out[2]
p2_out[3] <= I8051_RAM:U_RAM.p2_out[3]
p2_out[4] <= I8051_RAM:U_RAM.p2_out[4]
p2_out[5] <= I8051_RAM:U_RAM.p2_out[5]
p2_out[6] <= I8051_RAM:U_RAM.p2_out[6]
p2_out[7] <= I8051_RAM:U_RAM.p2_out[7]
p3_in[0] => I8051_RAM:U_RAM.p3_in[0]
p3_in[1] => I8051_RAM:U_RAM.p3_in[1]
p3_in[2] => I8051_RAM:U_RAM.p3_in[2]
p3_in[3] => I8051_RAM:U_RAM.p3_in[3]
p3_in[4] => I8051_RAM:U_RAM.p3_in[4]
p3_in[5] => I8051_RAM:U_RAM.p3_in[5]
p3_in[6] => I8051_RAM:U_RAM.p3_in[6]
p3_in[7] => I8051_RAM:U_RAM.p3_in[7]
p3_out[0] <= I8051_RAM:U_RAM.p3_out[0]
p3_out[1] <= I8051_RAM:U_RAM.p3_out[1]
p3_out[2] <= I8051_RAM:U_RAM.p3_out[2]
p3_out[3] <= I8051_RAM:U_RAM.p3_out[3]
p3_out[4] <= I8051_RAM:U_RAM.p3_out[4]
p3_out[5] <= I8051_RAM:U_RAM.p3_out[5]
p3_out[6] <= I8051_RAM:U_RAM.p3_out[6]
p3_out[7] <= I8051_RAM:U_RAM.p3_out[7]


|i8051_all|I8051_ALU:U_ALU
rst => ~NO_FANOUT~
op_code[0] => Mux17.IN5
op_code[0] => Mux15.IN5
op_code[0] => Mux14.IN5
op_code[0] => Mux13.IN5
op_code[0] => Mux12.IN5
op_code[0] => Mux11.IN5
op_code[0] => Mux10.IN5
op_code[0] => Mux9.IN5
op_code[0] => Mux8.IN5
op_code[0] => Mux7.IN14
op_code[0] => Mux6.IN15
op_code[0] => Mux5.IN15
op_code[0] => Mux4.IN15
op_code[0] => Mux3.IN15
op_code[0] => Mux2.IN15
op_code[0] => Mux1.IN15
op_code[0] => Mux0.IN15
op_code[1] => Mux17.IN4
op_code[1] => des_ac~0.OUTPUTSELECT
op_code[1] => Mux16.IN8
op_code[1] => Mux7.IN13
op_code[1] => Mux6.IN14
op_code[1] => Mux5.IN14
op_code[1] => Mux4.IN14
op_code[1] => Mux3.IN14
op_code[1] => Mux2.IN14
op_code[1] => Mux1.IN14
op_code[1] => Mux0.IN14
op_code[2] => Mux16.IN7
op_code[2] => Mux7.IN12
op_code[2] => Mux6.IN13
op_code[2] => Mux5.IN13
op_code[2] => Mux4.IN13
op_code[2] => Mux3.IN13
op_code[2] => Mux2.IN13
op_code[2] => Mux1.IN13
op_code[2] => Mux0.IN13
op_code[3] => Mux16.IN6
op_code[3] => Mux15.IN4
op_code[3] => Mux14.IN4
op_code[3] => Mux13.IN4
op_code[3] => Mux12.IN4
op_code[3] => Mux11.IN4
op_code[3] => Mux10.IN4
op_code[3] => Mux9.IN4
op_code[3] => Mux8.IN4
op_code[3] => Mux7.IN11
op_code[3] => Mux6.IN12
op_code[3] => Mux5.IN12
op_code[3] => Mux4.IN12
op_code[3] => Mux3.IN12
op_code[3] => Mux2.IN12
op_code[3] => Mux1.IN12
op_code[3] => Mux0.IN12
src_1[0] => Mux16.IN10
src_1[0] => Mux7.IN18
src_1[0] => Mux6.IN18
src_1[0] => Mux6.IN19
src_1[0] => Mux0.IN18
src_1[0] => Add23.IN16
src_1[0] => Add22.IN8
src_1[0] => des_1~23.IN0
src_1[0] => des_1~15.IN0
src_1[0] => des_1~7.IN0
src_1[0] => LessThan1.IN8
src_1[0] => r~7.DATAB
src_1[0] => v1~56.DATAA
src_1[0] => Add19.IN16
src_1[0] => LessThan0.IN8
src_1[0] => Equal2.IN7
src_1[0] => Mult0.IN7
src_1[0] => Add6.IN8
src_1[0] => Add0.IN4
src_1[0] => Mux7.IN5
src_1[1] => Mux7.IN16
src_1[1] => Mux7.IN17
src_1[1] => Mux5.IN18
src_1[1] => Mux5.IN19
src_1[1] => Add23.IN15
src_1[1] => Add22.IN7
src_1[1] => des_1~22.IN0
src_1[1] => des_1~14.IN0
src_1[1] => des_1~6.IN0
src_1[1] => v~7.DATAA
src_1[1] => Add20.IN14
src_1[1] => LessThan1.IN7
src_1[1] => r~6.DATAB
src_1[1] => v1~48.DATAA
src_1[1] => Add18.IN16
src_1[1] => LessThan0.IN7
src_1[1] => Equal2.IN6
src_1[1] => Mult0.IN6
src_1[1] => Add6.IN7
src_1[1] => Add0.IN3
src_1[1] => Mux6.IN6
src_1[2] => Mux6.IN16
src_1[2] => Mux6.IN17
src_1[2] => Mux4.IN18
src_1[2] => Mux4.IN19
src_1[2] => Add23.IN14
src_1[2] => Add22.IN6
src_1[2] => des_1~21.IN0
src_1[2] => des_1~13.IN0
src_1[2] => des_1~5.IN0
src_1[2] => v~6.DATAA
src_1[2] => Add20.IN13
src_1[2] => LessThan1.IN6
src_1[2] => r~5.DATAB
src_1[2] => v1~41.DATAA
src_1[2] => Add17.IN16
src_1[2] => LessThan0.IN6
src_1[2] => Equal2.IN5
src_1[2] => Mult0.IN5
src_1[2] => Add6.IN6
src_1[2] => Add0.IN2
src_1[2] => Mux5.IN6
src_1[3] => Mux5.IN16
src_1[3] => Mux5.IN17
src_1[3] => Mux3.IN18
src_1[3] => Mux3.IN19
src_1[3] => Add23.IN13
src_1[3] => Add22.IN5
src_1[3] => des_1~20.IN0
src_1[3] => des_1~12.IN0
src_1[3] => des_1~4.IN0
src_1[3] => v~5.DATAA
src_1[3] => Add20.IN12
src_1[3] => LessThan1.IN5
src_1[3] => r~4.DATAB
src_1[3] => v1~34.DATAA
src_1[3] => Add16.IN16
src_1[3] => LessThan0.IN5
src_1[3] => Equal2.IN4
src_1[3] => Mult0.IN4
src_1[3] => Add6.IN5
src_1[3] => Add0.IN1
src_1[3] => Mux4.IN6
src_1[4] => Mux4.IN16
src_1[4] => Mux4.IN17
src_1[4] => Mux2.IN18
src_1[4] => Mux2.IN19
src_1[4] => Add23.IN12
src_1[4] => Add22.IN4
src_1[4] => des_1~19.IN0
src_1[4] => des_1~11.IN0
src_1[4] => des_1~3.IN0
src_1[4] => v~4.DATAA
src_1[4] => Add20.IN11
src_1[4] => r~3.DATAB
src_1[4] => v1~27.DATAA
src_1[4] => Add15.IN16
src_1[4] => LessThan0.IN4
src_1[4] => Equal2.IN3
src_1[4] => Mult0.IN3
src_1[4] => Add8.IN6
src_1[4] => Add2.IN3
src_1[4] => Mux3.IN6
src_1[5] => Mux3.IN16
src_1[5] => Mux3.IN17
src_1[5] => Mux1.IN18
src_1[5] => Mux1.IN19
src_1[5] => Add23.IN11
src_1[5] => Add22.IN3
src_1[5] => des_1~18.IN0
src_1[5] => des_1~10.IN0
src_1[5] => des_1~2.IN0
src_1[5] => v~3.DATAA
src_1[5] => Add20.IN10
src_1[5] => r~2.DATAB
src_1[5] => v1~20.DATAA
src_1[5] => Add14.IN16
src_1[5] => LessThan0.IN3
src_1[5] => Equal2.IN2
src_1[5] => Mult0.IN2
src_1[5] => Add8.IN5
src_1[5] => Add2.IN2
src_1[5] => Mux2.IN6
src_1[6] => Mux2.IN16
src_1[6] => Mux2.IN17
src_1[6] => Mux0.IN16
src_1[6] => Mux0.IN17
src_1[6] => Add23.IN10
src_1[6] => Add22.IN2
src_1[6] => des_1~17.IN0
src_1[6] => des_1~9.IN0
src_1[6] => des_1~1.IN0
src_1[6] => v~2.DATAA
src_1[6] => Add20.IN9
src_1[6] => r~1.DATAB
src_1[6] => v1~13.DATAA
src_1[6] => Add13.IN16
src_1[6] => LessThan0.IN2
src_1[6] => Equal2.IN1
src_1[6] => Mult0.IN1
src_1[6] => Add8.IN4
src_1[6] => Add2.IN1
src_1[6] => Mux1.IN6
src_1[7] => Mux16.IN9
src_1[7] => Mux7.IN15
src_1[7] => Mux1.IN16
src_1[7] => Mux1.IN17
src_1[7] => Add23.IN9
src_1[7] => Add22.IN1
src_1[7] => des_1~16.IN0
src_1[7] => des_1~8.IN0
src_1[7] => des_1~0.IN0
src_1[7] => v~1.DATAA
src_1[7] => Add20.IN8
src_1[7] => r~0.DATAB
src_1[7] => v1~6.DATAA
src_1[7] => Add12.IN16
src_1[7] => LessThan0.IN1
src_1[7] => Equal2.IN0
src_1[7] => Mult0.IN0
src_1[7] => Add10.IN2
src_1[7] => Add4.IN1
src_1[7] => Mux0.IN6
src_2[0] => Add23.IN24
src_2[0] => Add22.IN16
src_2[0] => des_1~23.IN1
src_2[0] => des_1~15.IN1
src_2[0] => des_1~7.IN1
src_2[0] => LessThan0.IN16
src_2[0] => Equal2.IN15
src_2[0] => Equal1.IN15
src_2[0] => Mult0.IN15
src_2[0] => Add0.IN8
src_2[0] => Add19.IN8
src_2[0] => Add18.IN8
src_2[0] => Add17.IN8
src_2[0] => Add16.IN8
src_2[0] => Add15.IN8
src_2[0] => Add14.IN8
src_2[0] => Add13.IN8
src_2[0] => Add6.IN4
src_2[0] => Add12.IN15
src_2[1] => Add23.IN23
src_2[1] => Add22.IN15
src_2[1] => des_1~22.IN1
src_2[1] => des_1~14.IN1
src_2[1] => des_1~6.IN1
src_2[1] => LessThan0.IN15
src_2[1] => Equal2.IN14
src_2[1] => Equal1.IN14
src_2[1] => Mult0.IN14
src_2[1] => Add0.IN7
src_2[1] => Add19.IN7
src_2[1] => Add18.IN7
src_2[1] => Add17.IN7
src_2[1] => Add16.IN7
src_2[1] => Add15.IN7
src_2[1] => Add14.IN7
src_2[1] => Add13.IN7
src_2[1] => Add6.IN3
src_2[1] => Add12.IN14
src_2[2] => Add23.IN22
src_2[2] => Add22.IN14
src_2[2] => des_1~21.IN1
src_2[2] => des_1~13.IN1
src_2[2] => des_1~5.IN1
src_2[2] => LessThan0.IN14
src_2[2] => Equal2.IN13
src_2[2] => Equal1.IN13
src_2[2] => Mult0.IN13
src_2[2] => Add0.IN6
src_2[2] => Add19.IN6
src_2[2] => Add18.IN6
src_2[2] => Add17.IN6
src_2[2] => Add16.IN6
src_2[2] => Add15.IN6
src_2[2] => Add14.IN6
src_2[2] => Add13.IN6
src_2[2] => Add6.IN2
src_2[2] => Add12.IN13
src_2[3] => Add23.IN21
src_2[3] => Add22.IN13
src_2[3] => des_1~20.IN1
src_2[3] => des_1~12.IN1
src_2[3] => des_1~4.IN1
src_2[3] => LessThan0.IN13
src_2[3] => Equal2.IN12
src_2[3] => Equal1.IN12
src_2[3] => Mult0.IN12
src_2[3] => Add0.IN5
src_2[3] => Add19.IN5
src_2[3] => Add18.IN5
src_2[3] => Add17.IN5
src_2[3] => Add16.IN5
src_2[3] => Add15.IN5
src_2[3] => Add14.IN5
src_2[3] => Add13.IN5
src_2[3] => Add6.IN1
src_2[3] => Add12.IN12
src_2[4] => Add23.IN20
src_2[4] => Add22.IN12
src_2[4] => des_1~19.IN1
src_2[4] => des_1~11.IN1
src_2[4] => des_1~3.IN1
src_2[4] => LessThan0.IN12
src_2[4] => Equal2.IN11
src_2[4] => Equal1.IN11
src_2[4] => Mult0.IN11
src_2[4] => Add2.IN6
src_2[4] => Add19.IN4
src_2[4] => Add18.IN4
src_2[4] => Add17.IN4
src_2[4] => Add16.IN4
src_2[4] => Add15.IN4
src_2[4] => Add14.IN4
src_2[4] => Add13.IN4
src_2[4] => Add8.IN3
src_2[4] => Add12.IN11
src_2[5] => Add23.IN19
src_2[5] => Add22.IN11
src_2[5] => des_1~18.IN1
src_2[5] => des_1~10.IN1
src_2[5] => des_1~2.IN1
src_2[5] => LessThan0.IN11
src_2[5] => Equal2.IN10
src_2[5] => Equal1.IN10
src_2[5] => Mult0.IN10
src_2[5] => Add2.IN5
src_2[5] => Add19.IN3
src_2[5] => Add18.IN3
src_2[5] => Add17.IN3
src_2[5] => Add16.IN3
src_2[5] => Add15.IN3
src_2[5] => Add14.IN3
src_2[5] => Add13.IN3
src_2[5] => Add8.IN2
src_2[5] => Add12.IN10
src_2[6] => Add23.IN18
src_2[6] => Add22.IN10
src_2[6] => des_1~17.IN1
src_2[6] => des_1~9.IN1
src_2[6] => des_1~1.IN1
src_2[6] => LessThan0.IN10
src_2[6] => Equal2.IN9
src_2[6] => Equal1.IN9
src_2[6] => Mult0.IN9
src_2[6] => Add2.IN4
src_2[6] => Add19.IN2
src_2[6] => Add18.IN2
src_2[6] => Add17.IN2
src_2[6] => Add16.IN2
src_2[6] => Add15.IN2
src_2[6] => Add14.IN2
src_2[6] => Add13.IN2
src_2[6] => Add8.IN1
src_2[6] => Add12.IN9
src_2[7] => Add23.IN17
src_2[7] => Add22.IN9
src_2[7] => des_1~16.IN1
src_2[7] => des_1~8.IN1
src_2[7] => des_1~0.IN1
src_2[7] => LessThan0.IN9
src_2[7] => Equal2.IN8
src_2[7] => Equal1.IN8
src_2[7] => Mult0.IN8
src_2[7] => Add4.IN2
src_2[7] => Add19.IN1
src_2[7] => Add18.IN1
src_2[7] => Add17.IN1
src_2[7] => Add16.IN1
src_2[7] => Add15.IN1
src_2[7] => Add14.IN1
src_2[7] => Add13.IN1
src_2[7] => Add10.IN1
src_2[7] => Add12.IN8
src_3[0] => Add23.IN32
src_3[0] => Add22.IN32
src_3[1] => Add23.IN31
src_3[1] => Add22.IN31
src_3[2] => Add23.IN30
src_3[2] => Add22.IN30
src_3[3] => Add23.IN29
src_3[3] => Add22.IN29
src_3[4] => Add23.IN28
src_3[4] => Add22.IN28
src_3[5] => Add23.IN27
src_3[5] => Add22.IN27
src_3[6] => Add23.IN26
src_3[6] => Add22.IN26
src_3[7] => Add22.IN17
src_3[7] => Add22.IN18
src_3[7] => Add22.IN19
src_3[7] => Add22.IN20
src_3[7] => Add22.IN21
src_3[7] => Add22.IN22
src_3[7] => Add22.IN23
src_3[7] => Add22.IN24
src_3[7] => Add23.IN25
src_3[7] => Add22.IN25
src_cy => Mux7.IN19
src_cy => Mux0.IN19
src_cy => v~8.IN0
src_cy => Add1.IN10
src_cy => Add7.IN10
src_ac => DO_DA~0.IN1
des_1[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
des_1[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
des_1[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
des_1[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
des_1[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
des_1[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE