i8051_all.hif

8051的vhdl源代码

Version 7.1 Build 156 04/30/2007 SJ Full Version
11
853
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
synplcty.lmf
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
I8051_ALU
# storage
db|i8051_all.(1).cnf
db|i8051_all.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
I8051_ALU.vhd
813d2bc5dcb1a1904b7b12c586ab42
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(op_code)
3 downto 0
PARAMETER_STRING
USR
 constraint(src_1)
7 downto 0
PARAMETER_STRING
USR
 constraint(src_2)
7 downto 0
PARAMETER_STRING
USR
 constraint(src_3)
7 downto 0
PARAMETER_STRING
USR
 constraint(des_1)
7 downto 0
PARAMETER_STRING
USR
 constraint(des_2)
7 downto 0
PARAMETER_STRING
USR
}
# include_file {
C:|altera|71|quartus|libraries|vhdl|work|i8051_lib.vhd
28e53999cff02e9cc4e2c9e21fa7e45
}
# hierarchies {
I8051_ALU:U_ALU
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
I8051_DEC
# storage
db|i8051_all.(2).cnf
db|i8051_all.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
I8051_DEC.vhd
73a4b916cfd0c3eac8781f16f3c1f8f0
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(op_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(op_out)
8 downto 0
PARAMETER_STRING
USR
}
# include_file {
C:|altera|71|quartus|libraries|vhdl|work|i8051_lib.vhd
28e53999cff02e9cc4e2c9e21fa7e45
}
# hierarchies {
I8051_DEC:U_DEC
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
I8051_RAM
# storage
db|i8051_all.(3).cnf
db|i8051_all.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
I8051_RAM.vhd
e5b04c3bcdb4d6fa6f5dd91e79d142e
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(addr)
7 downto 0
PARAMETER_STRING
USR
 constraint(in_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(out_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(p0_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(p0_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(p1_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(p1_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(p2_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(p2_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(p3_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(p3_out)
7 downto 0
PARAMETER_STRING
USR
}
# include_file {
C:|altera|71|quartus|libraries|vhdl|work|i8051_lib.vhd
28e53999cff02e9cc4e2c9e21fa7e45
}
# hierarchies {
I8051_RAM:U_RAM
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
I8051_ROM
# storage
db|i8051_all.(4).cnf
db|i8051_all.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
I8051_ROM.vhd
1be2e89b801f14adb8cd4a86f44ba
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(addr)
11 downto 0
PARAMETER_STRING
USR
 constraint(data)
7 downto 0
PARAMETER_STRING
USR
}
# include_file {
C:|altera|71|quartus|libraries|vhdl|work|i8051_lib.vhd
28e53999cff02e9cc4e2c9e21fa7e45
}
# hierarchies {
I8051_ROM:U_ROM
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
I8051_CTR
# storage
db|i8051_all.(5).cnf
db|i8051_all.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
I8051_CTR.vhd
359cdeebf12e68a2f9c4101c5e173334
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(rom_addr)
11 downto 0
PARAMETER_STRING
USR
 constraint(rom_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(ram_addr)
7 downto 0
PARAMETER_STRING
USR
 constraint(ram_out_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(ram_in_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(xrm_addr)
15 downto 0
PARAMETER_STRING
USR
 constraint(xrm_out_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(xrm_in_data)
7 downto 0
PARAMETER_STRING
USR
 constraint(dec_op_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(dec_op_in)
8 downto 0
PARAMETER_STRING
USR
 constraint(alu_op_code)
3 downto 0
PARAMETER_STRING
USR
 constraint(alu_src_1)
7 downto 0
PARAMETER_STRING
USR
 constraint(alu_src_2)
7 downto 0
PARAMETER_STRING
USR
 constraint(alu_src_3)
7 downto 0
PARAMETER_STRING
USR
 constraint(alu_des_1)
7 downto 0
PARAMETER_STRING
USR
 constraint(alu_des_2)
7 downto 0
PARAMETER_STRING
USR
}
# include_file {
C:|altera|71|quartus|libraries|vhdl|work|i8051_lib.vhd
28e53999cff02e9cc4e2c9e21fa7e45
}
# hierarchies {
I8051_CTR:U_CTR
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
I8051_DBG
# storage
db|i8051_all.(6).cnf
db|i8051_all.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
I8051_DBG.vhd
7eb159680dfd4ab4247edbb7dacb327
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(op_in)
8 downto 0
PARAMETER_STRING
USR
}
# include_file {
C:|altera|71|quartus|libraries|vhdl|work|i8051_lib.vhd
28e53999cff02e9cc4e2c9e21fa7e45
}
# hierarchies {
I8051_DBG:U_DBG
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
altsyncram
# storage
db|i8051_all.(7).cnf
db|i8051_all.(7).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|altsyncram.tdf
b69478c2691550fb7f5ef3923da937a
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
10
PARAMETER_UNKNOWN
USR
NUMWORDS_A
1024
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
I8051_ALL0.rtl.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_pnu
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|71|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|71|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|71|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|71|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|71|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
c:|altera|71|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# lmf
c:|altera|71|quartus|lmf|synplcty.lmf
decdce24f1a7b64de7c1e213c55bab
# macro_sequence

# end
# entity
altsyncram_pnu
# storage
db|i8051_all.(8).cnf
db|i8051_all.(8).cnf
# case_insensitive
# source_file
db|altsyncram_pnu.tdf
5f7fcee97e58a287e8abe09c1827135d
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
I8051_ALL0.rtl.mif
32c6f1d3e288b2ef5dbf9229d517409d
}
# lmf
c:|altera|71|quartus|lmf|synplcty.lmf
decdce24f1a7b64de7c1e213c55bab
# macro_sequence

# end
# entity
lpm_mult
# storage
db|i8051_all.(9).cnf
db|i8051_all.(9).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|lpm_mult.tdf
405065fceca1fb710a566a7c655524
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTHA
8
PARAMETER_UNKNOWN
USR
LPM_WIDTHB
8
PARAMETER_UNKNOWN
USR
LPM_WIDTHP
16
PARAMETER_UNKNOWN
USR
LPM_WIDTHR
16
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_A_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
INPUT_B_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
APEX20K_TECHNOLOGY_MAPPER
LUT
TECH_MAPPER_APEX20K
USR
DEDICATED_MULTIPLIER_CIRCUITRY
AUTO
PARAMETER_UNKNOWN
USR
DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_cs01
PARAMETER_UNKNOWN
USR
INPUT_A_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
INPUT_B_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
USE_AHDL_IMPLEMENTATION
OFF
PARAMETER_UNKNOWN
DEF
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
c:|altera|71|quartus|libraries|megafunctions|multcore.inc
13b7e8bee916e23c5f79837e9c670
c:|altera|71|quartus|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
c:|altera|71|quartus|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
}
# lmf
c:|altera|71|quartus|lmf|synplcty.lmf
decdce24f1a7b64de7c1e213c55bab
# macro_sequence

# end
# entity
mult_cs01
# storage
db|i8051_all.(10).cnf
db|i8051_all.(10).cnf
# case_insensitive
# source_file
db|mult_cs01.tdf
c68199295996aeea28b7ed0828998b1
6
# user_parameter {
dataa_width
0
PARAMETER_UNKNOWN
DEF
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# lmf
c:|altera|71|quartus|lmf|synplcty.lmf
decdce24f1a7b64de7c1e213c55bab
# macro_sequence

# end
# entity
i8051_all
# storage
db|i8051_all.(0).cnf
db|i8051_all.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
i8051_all.vhd
2488fc5cf3797a9158d9b5b41d14c84c
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# include_file {
C:|altera|71|quartus|libraries|vhdl|work|i8051_lib.vhd
28e53999cff02e9cc4e2c9e21fa7e45
}
# hierarchies {
|
}
# lmf
c:|altera|71|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# complete