prev_cmp_i8051_all.qmsg

8051的vhdl源代码

{ "Warning" "WSGN_SEARCH_FILE" "I8051_RAM.vhd 2 1 " "Warning: Using design file I8051_RAM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 I8051_RAM-BHV " "Info: Found design unit 1: I8051_RAM-BHV" {  } { { "I8051_RAM.vhd" "" { Text "D:/8051/I8051_RAM.vhd" 61 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 I8051_RAM " "Info: Found entity 1: I8051_RAM" {  } { { "I8051_RAM.vhd" "" { Text "D:/8051/I8051_RAM.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I8051_RAM I8051_RAM:U_RAM " "Info: Elaborating entity \"I8051_RAM\" for hierarchy \"I8051_RAM:U_RAM\"" {  } { { "i8051_all.vhd" "U_RAM" { Text "D:/8051/i8051_all.vhd" 191 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "I8051_ROM.vhd 2 1 " "Warning: Using design file I8051_ROM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 I8051_ROM-BHV " "Info: Found design unit 1: I8051_ROM-BHV" {  } { { "I8051_ROM.vhd" "" { Text "D:/8051/I8051_ROM.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 I8051_ROM " "Info: Found entity 1: I8051_ROM" {  } { { "I8051_ROM.vhd" "" { Text "D:/8051/I8051_ROM.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I8051_ROM I8051_ROM:U_ROM " "Info: Elaborating entity \"I8051_ROM\" for hierarchy \"I8051_ROM:U_ROM\"" {  } { { "i8051_all.vhd" "U_ROM" { Text "D:/8051/i8051_all.vhd" 210 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "I8051_CTR.vhd 2 1 " "Warning: Using design file I8051_CTR.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 I8051_CTR-BHV " "Info: Found design unit 1: I8051_CTR-BHV" {  } { { "I8051_CTR.vhd" "" { Text "D:/8051/I8051_CTR.vhd" 89 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 I8051_CTR " "Info: Found entity 1: I8051_CTR" {  } { { "I8051_CTR.vhd" "" { Text "D:/8051/I8051_CTR.vhd" 53 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I8051_CTR I8051_CTR:U_CTR " "Info: Elaborating entity \"I8051_CTR\" for hierarchy \"I8051_CTR:U_CTR\"" {  } { { "i8051_all.vhd" "U_CTR" { Text "D:/8051/i8051_all.vhd" 216 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "I8051_DBG.vhd 2 1 " "Warning: Using design file I8051_DBG.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 I8051_DBG-BHV " "Info: Found design unit 1: I8051_DBG-BHV" {  } { { "I8051_DBG.vhd" "" { Text "D:/8051/I8051_DBG.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 I8051_DBG " "Info: Found entity 1: I8051_DBG" {  } { { "I8051_DBG.vhd" "" { Text "D:/8051/I8051_DBG.vhd" 22 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I8051_DBG I8051_DBG:U_DBG " "Info: Elaborating entity \"I8051_DBG\" for hierarchy \"I8051_DBG:U_DBG\"" {  } { { "i8051_all.vhd" "U_DBG" { Text "D:/8051/i8051_all.vhd" 249 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "opc I8051_DBG.vhd(145) " "Warning (10036): Verilog HDL or VHDL warning at I8051_DBG.vhd(145): object \"opc\" assigned a value but never read" {  } { { "I8051_DBG.vhd" "" { Text "D:/8051/I8051_DBG.vhd" 145 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|I8051_ALL\|I8051_CTR:U_CTR\|exe_state 8 " "Info: State machine \"\|I8051_ALL\|I8051_CTR:U_CTR\|exe_state\" contains 8 states" {  } { { "I8051_CTR.vhd" "" { Text "D:/8051/I8051_CTR.vhd" 111 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}