📄 i8051_all.tan.rpt
字号:
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 26.00 MHz ( period = 38.468 ns ) ; I8051_CTR:U_CTR|alu_src_1[7] ; I8051_CTR:U_CTR|alu_src_3[5] ; clk ; clk ; None ; None ; 38.211 ns ;
; N/A ; 26.00 MHz ( period = 38.464 ns ) ; I8051_CTR:U_CTR|alu_src_1[7] ; I8051_CTR:U_CTR|alu_src_3[7] ; clk ; clk ; None ; None ; 38.207 ns ;
; N/A ; 26.03 MHz ( period = 38.418 ns ) ; I8051_CTR:U_CTR|alu_src_2[0]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[5] ; clk ; clk ; None ; None ; 38.161 ns ;
; N/A ; 26.03 MHz ( period = 38.414 ns ) ; I8051_CTR:U_CTR|alu_src_2[0]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[7] ; clk ; clk ; None ; None ; 38.157 ns ;
; N/A ; 26.08 MHz ( period = 38.339 ns ) ; I8051_CTR:U_CTR|alu_src_2[1]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[5] ; clk ; clk ; None ; None ; 38.082 ns ;
; N/A ; 26.09 MHz ( period = 38.335 ns ) ; I8051_CTR:U_CTR|alu_src_2[1]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[7] ; clk ; clk ; None ; None ; 38.078 ns ;
; N/A ; 26.14 MHz ( period = 38.259 ns ) ; I8051_CTR:U_CTR|alu_src_2[2]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[5] ; clk ; clk ; None ; None ; 38.002 ns ;
; N/A ; 26.14 MHz ( period = 38.255 ns ) ; I8051_CTR:U_CTR|alu_src_2[2]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[7] ; clk ; clk ; None ; None ; 37.998 ns ;
; N/A ; 26.20 MHz ( period = 38.169 ns ) ; I8051_CTR:U_CTR|alu_src_1[7] ; I8051_CTR:U_CTR|alu_src_3[1] ; clk ; clk ; None ; None ; 37.912 ns ;
; N/A ; 26.20 MHz ( period = 38.164 ns ) ; I8051_CTR:U_CTR|alu_src_1[7] ; I8051_CTR:U_CTR|alu_src_3[2] ; clk ; clk ; None ; None ; 37.907 ns ;
; N/A ; 26.20 MHz ( period = 38.161 ns ) ; I8051_CTR:U_CTR|alu_src_1[7] ; I8051_CTR:U_CTR|alu_src_3[4] ; clk ; clk ; None ; None ; 37.904 ns ;
; N/A ; 26.21 MHz ( period = 38.159 ns ) ; I8051_CTR:U_CTR|alu_src_1[7] ; I8051_CTR:U_CTR|alu_src_3[3] ; clk ; clk ; None ; None ; 37.902 ns ;
; N/A ; 26.21 MHz ( period = 38.156 ns ) ; I8051_CTR:U_CTR|alu_src_1[7] ; I8051_CTR:U_CTR|alu_src_3[6] ; clk ; clk ; None ; None ; 37.899 ns ;
; N/A ; 26.23 MHz ( period = 38.119 ns ) ; I8051_CTR:U_CTR|alu_src_2[0]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[1] ; clk ; clk ; None ; None ; 37.862 ns ;
; N/A ; 26.24 MHz ( period = 38.114 ns ) ; I8051_CTR:U_CTR|alu_src_2[0]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[2] ; clk ; clk ; None ; None ; 37.857 ns ;
; N/A ; 26.24 MHz ( period = 38.111 ns ) ; I8051_CTR:U_CTR|alu_src_2[0]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[4] ; clk ; clk ; None ; None ; 37.854 ns ;
; N/A ; 26.24 MHz ( period = 38.109 ns ) ; I8051_CTR:U_CTR|alu_src_2[0]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[3] ; clk ; clk ; None ; None ; 37.852 ns ;
; N/A ; 26.24 MHz ( period = 38.106 ns ) ; I8051_CTR:U_CTR|alu_src_2[0]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[6] ; clk ; clk ; None ; None ; 37.849 ns ;
; N/A ; 26.27 MHz ( period = 38.073 ns ) ; I8051_CTR:U_CTR|alu_src_2[6]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[5] ; clk ; clk ; None ; None ; 37.816 ns ;
; N/A ; 26.27 MHz ( period = 38.069 ns ) ; I8051_CTR:U_CTR|alu_src_2[6]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[7] ; clk ; clk ; None ; None ; 37.812 ns ;
; N/A ; 26.27 MHz ( period = 38.065 ns ) ; I8051_CTR:U_CTR|alu_src_2[3]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[5] ; clk ; clk ; None ; None ; 37.808 ns ;
; N/A ; 26.27 MHz ( period = 38.061 ns ) ; I8051_CTR:U_CTR|alu_src_2[3]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[7] ; clk ; clk ; None ; None ; 37.804 ns ;
; N/A ; 26.29 MHz ( period = 38.040 ns ) ; I8051_CTR:U_CTR|alu_src_2[1]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[1] ; clk ; clk ; None ; None ; 37.783 ns ;
; N/A ; 26.29 MHz ( period = 38.035 ns ) ; I8051_CTR:U_CTR|alu_src_2[1]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[2] ; clk ; clk ; None ; None ; 37.778 ns ;
; N/A ; 26.29 MHz ( period = 38.032 ns ) ; I8051_CTR:U_CTR|alu_src_2[1]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[4] ; clk ; clk ; None ; None ; 37.775 ns ;
; N/A ; 26.30 MHz ( period = 38.030 ns ) ; I8051_CTR:U_CTR|alu_src_2[1]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[3] ; clk ; clk ; None ; None ; 37.773 ns ;
; N/A ; 26.30 MHz ( period = 38.027 ns ) ; I8051_CTR:U_CTR|alu_src_2[1]~_Duplicate_1 ; I8051_CTR:U_CTR|alu_src_3[6] ; clk ; clk ; None ; None ; 37.770 ns ;
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