div.vhd

8051的vhdl源代码

	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1549w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1525w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1527w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1529w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1531w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1533w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1535w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1537w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1539w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_rom_mux_w_range1541w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 COMPONENT  div_adder_block_vca
	 PORT
	 ( 
		adder_var	:	IN  STD_LOGIC;
		divider_next	:	OUT  STD_LOGIC_VECTOR(23 DOWNTO 0);
		divider_reg	:	IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
		neg_qkd_reg	:	IN  STD_LOGIC_VECTOR(26 DOWNTO 0);
		Rk_next	:	OUT  STD_LOGIC_VECTOR(24 DOWNTO 0);
		Rk_reg	:	IN  STD_LOGIC_VECTOR(24 DOWNTO 0)
	 ); 
	 END COMPONENT;
	 COMPONENT  div_adder_last_block_ita
	 PORT
	 ( 
		adder_var	:	IN  STD_LOGIC;
		divider_next	:	OUT  STD_LOGIC_VECTOR(23 DOWNTO 0);
		divider_reg	:	IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
		neg_qkd_reg	:	IN  STD_LOGIC_VECTOR(26 DOWNTO 0);
		Rk_next	:	OUT  STD_LOGIC_VECTOR(26 DOWNTO 0);
		Rk_reg	:	IN  STD_LOGIC_VECTOR(24 DOWNTO 0)
	 ); 
	 END COMPONENT;
	 COMPONENT  altsyncram
	 GENERIC 
	 (
		ADDRESS_ACLR_A	:	STRING := "UNUSED";
		ADDRESS_ACLR_B	:	STRING := "NONE";
		ADDRESS_REG_B	:	STRING := "CLOCK1";
		BYTE_SIZE	:	NATURAL := 8;
		BYTEENA_ACLR_A	:	STRING := "UNUSED";
		BYTEENA_ACLR_B	:	STRING := "NONE";
		BYTEENA_REG_B	:	STRING := "CLOCK1";
		CLOCK_ENABLE_CORE_A	:	STRING := "USE_INPUT_CLKEN";
		CLOCK_ENABLE_CORE_B	:	STRING := "USE_INPUT_CLKEN";
		CLOCK_ENABLE_INPUT_A	:	STRING := "NORMAL";
		CLOCK_ENABLE_INPUT_B	:	STRING := "NORMAL";
		CLOCK_ENABLE_OUTPUT_A	:	STRING := "NORMAL";
		CLOCK_ENABLE_OUTPUT_B	:	STRING := "NORMAL";
		ENABLE_ECC	:	STRING := "FALSE";
		IMPLEMENT_IN_LES	:	STRING := "OFF";
		INDATA_ACLR_A	:	STRING := "UNUSED";
		INDATA_ACLR_B	:	STRING := "NONE";
		INDATA_REG_B	:	STRING := "CLOCK1";
		INIT_FILE	:	STRING := "UNUSED";
		INIT_FILE_LAYOUT	:	STRING := "PORT_A";
		MAXIMUM_DEPTH	:	NATURAL := 0;
		NUMWORDS_A	:	NATURAL := 0;
		NUMWORDS_B	:	NATURAL := 0;
		OPERATION_MODE	:	STRING := "BIDIR_DUAL_PORT";
		OUTDATA_ACLR_A	:	STRING := "NONE";
		OUTDATA_ACLR_B	:	STRING := "NONE";
		OUTDATA_REG_A	:	STRING := "UNREGISTERED";
		OUTDATA_REG_B	:	STRING := "UNREGISTERED";
		POWER_UP_UNINITIALIZED	:	STRING := "FALSE";
		RAM_BLOCK_TYPE	:	STRING := "AUTO";
		RDCONTROL_ACLR_B	:	STRING := "NONE";
		RDCONTROL_REG_B	:	STRING := "CLOCK1";
		READ_DURING_WRITE_MODE_MIXED_PORTS	:	STRING := "DONT_CARE";
		read_during_write_mode_port_a	:	STRING := "NEW_DATA_NO_NBE_READ";
		read_during_write_mode_port_b	:	STRING := "NEW_DATA_NO_NBE_READ";
		WIDTH_A	:	NATURAL;
		WIDTH_B	:	NATURAL := 1;
		WIDTH_BYTEENA_A	:	NATURAL := 1;
		WIDTH_BYTEENA_B	:	NATURAL := 1;
		WIDTHAD_A	:	NATURAL;
		WIDTHAD_B	:	NATURAL := 1;
		WRCONTROL_ACLR_A	:	STRING := "UNUSED";
		WRCONTROL_ACLR_B	:	STRING := "NONE";
		WRCONTROL_WRADDRESS_REG_B	:	STRING := "CLOCK1";
		INTENDED_DEVICE_FAMILY	:	STRING := "Cyclone II";
		lpm_hint	:	STRING := "UNUSED";
		lpm_type	:	STRING := "altsyncram"
	 );
	 PORT
	 ( 
		aclr0	:	IN STD_LOGIC := '0';
		aclr1	:	IN STD_LOGIC := '0';
		address_a	:	IN STD_LOGIC_VECTOR(WIDTHAD_A-1 DOWNTO 0);
		address_b	:	IN STD_LOGIC_VECTOR(WIDTHAD_B-1 DOWNTO 0) := (OTHERS => '1');
		addressstall_a	:	IN STD_LOGIC := '0';
		addressstall_b	:	IN STD_LOGIC := '0';
		byteena_a	:	IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_A-1 DOWNTO 0) := (OTHERS => '1');
		byteena_b	:	IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_B-1 DOWNTO 0) := (OTHERS => '1');
		clock0	:	IN STD_LOGIC := '1';
		clock1	:	IN STD_LOGIC := '1';
		clocken0	:	IN STD_LOGIC := '1';
		clocken1	:	IN STD_LOGIC := '1';
		clocken2	:	IN STD_LOGIC := '1';
		clocken3	:	IN STD_LOGIC := '1';
		data_a	:	IN STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0) := (OTHERS => '1');
		data_b	:	IN STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0) := (OTHERS => '1');
		eccstatus	:	OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
		q_a	:	OUT STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0);
		q_b	:	OUT STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0);
		rden_a	:	IN STD_LOGIC := '1';
		rden_b	:	IN STD_LOGIC := '1';
		wren_a	:	IN STD_LOGIC := '0';
		wren_b	:	IN STD_LOGIC := '0'
	 ); 
	 END COMPONENT;
	 COMPONENT  lpm_add_sub
	 GENERIC 
	 (
		LPM_DIRECTION	:	STRING := "DEFAULT";
		LPM_PIPELINE	:	NATURAL := 0;
		LPM_REPRESENTATION	:	STRING := "SIGNED";
		LPM_WIDTH	:	NATURAL;
		lpm_hint	:	STRING := "UNUSED";
		lpm_type	:	STRING := "lpm_add_sub"
	 );
	 PORT
	 ( 
		aclr	:	IN STD_LOGIC := '0';
		add_sub	:	IN STD_LOGIC := '1';
		cin	:	IN STD_LOGIC := 'Z';
		clken	:	IN STD_LOGIC := '1';
		clock	:	IN STD_LOGIC := '0';
		cout	:	OUT STD_LOGIC;
		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
		overflow	:	OUT STD_LOGIC;
		result	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
	 ); 
	 END COMPONENT;
	 COMPONENT  div_rom_block_f8k
	 PORT
	 ( 
		aclr	:	IN  STD_LOGIC := '0';
		adder_var	:	OUT  STD_LOGIC;
		clock	:	IN  STD_LOGIC := '0';
		divider	:	IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
		divider_reg	:	OUT  STD_LOGIC_VECTOR(23 DOWNTO 0);
		neg_qkd_reg	:	OUT  STD_LOGIC_VECTOR(26 DOWNTO 0);
		Rk	:	IN  STD_LOGIC_VECTOR(24 DOWNTO 0);
		Rk_reg	:	OUT  STD_LOGIC_VECTOR(24 DOWNTO 0);
		rom	:	OUT  STD_LOGIC_VECTOR(2 DOWNTO 0)
	 ); 
	 END COMPONENT;
 BEGIN

	loop10 : FOR i IN 0 TO 26 GENERATE 
		wire_altsrt_div1_w980w(i) <= wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w976w979w(0) AND divider_zeros_w(i);
	END GENERATE loop10;
	loop11 : FOR i IN 0 TO 26 GENERATE 
		wire_altsrt_div1_w978w(i) <= wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w976w977w(0) AND divider_1D_w(i);
	END GENERATE loop11;
	loop12 : FOR i IN 0 TO 26 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w974w975w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_int_w_range969w974w(0) AND divider_2D_w(i);
	END GENERATE loop12;
	loop13 : FOR i IN 0 TO 26 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w971w972w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_int_w_range969w971w(0) AND divider_1D_w(i);
	END GENERATE loop13;
	loop14 : FOR i IN 0 TO 27 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_mux_remainder_w1700w1704w(i) <= wire_altsrt_div1_w_lg_mux_remainder_w1700w(0) AND srt_adjust_w(i);
	END GENERATE loop14;
	loop15 : FOR i IN 0 TO 23 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_mux_remainder_w1700w1701w(i) <= wire_altsrt_div1_w_lg_mux_remainder_w1700w(0) AND wire_altsrt_div1_w_Rk_remainder_special_w_range1698w(i);
	END GENERATE loop15;
	wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w976w979w(0) <= wire_altsrt_div1_w_lg_w_rom_mux_int_w_range969w976w(0) AND wire_altsrt_div1_w_lg_w_rom_mux_int_w_range970w973w(0);
	wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w976w977w(0) <= wire_altsrt_div1_w_lg_w_rom_mux_int_w_range969w976w(0) AND wire_altsrt_div1_w_rom_mux_int_w_range970w(0);
	loop18 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1522w1552w1622w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1522w1552w(0) AND zero_quotient_w(i);
	END GENERATE loop18;
	loop19 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1522w1552w1553w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1522w1552w(0) AND wire_altsrt_div1_w_rom_dffe_w0c_range1551w(i);
	END GENERATE loop19;
	loop20 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1543w1602w1652w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1543w1602w(0) AND zero_quotient_w(i);
	END GENERATE loop20;
	loop21 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1543w1602w1603w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1543w1602w(0) AND wire_altsrt_div1_w_rom_dffe_w10c_range1601w(i);
	END GENERATE loop21;
	loop22 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1545w1607w1655w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1545w1607w(0) AND zero_quotient_w(i);
	END GENERATE loop22;
	loop23 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1545w1607w1608w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1545w1607w(0) AND wire_altsrt_div1_w_rom_dffe_w11c_range1606w(i);
	END GENERATE loop23;
	loop24 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1547w1612w1658w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1547w1612w(0) AND zero_quotient_w(i);
	END GENERATE loop24;
	loop25 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1547w1612w1613w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1547w1612w(0) AND wire_altsrt_div1_w_rom_dffe_w12c_range1611w(i);
	END GENERATE loop25;
	loop26 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1549w1617w1661w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1549w1617w(0) AND zero_quotient_w(i);
	END GENERATE loop26;
	loop27 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1549w1617w1618w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1549w1617w(0) AND wire_altsrt_div1_w_rom_dffe_w13c_range1616w(i);
	END GENERATE loop27;
	loop28 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1525w1557w1625w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1525w1557w(0) AND zero_quotient_w(i);
	END GENERATE loop28;
	loop29 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1525w1557w1558w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1525w1557w(0) AND wire_altsrt_div1_w_rom_dffe_w1c_range1556w(i);
	END GENERATE loop29;
	loop30 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1527w1562w1628w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1527w1562w(0) AND zero_quotient_w(i);
	END GENERATE loop30;
	loop31 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1527w1562w1563w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1527w1562w(0) AND wire_altsrt_div1_w_rom_dffe_w2c_range1561w(i);
	END GENERATE loop31;
	loop32 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1529w1567w1631w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1529w1567w(0) AND zero_quotient_w(i);
	END GENERATE loop32;
	loop33 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1529w1567w1568w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1529w1567w(0) AND wire_altsrt_div1_w_rom_dffe_w3c_range1566w(i);
	END GENERATE loop33;
	loop34 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1531w1572w1634w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1531w1572w(0) AND zero_quotient_w(i);
	END GENERATE loop34;
	loop35 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1531w1572w1573w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1531w1572w(0) AND wire_altsrt_div1_w_rom_dffe_w4c_range1571w(i);
	END GENERATE loop35;
	loop36 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1533w1577w1637w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1533w1577w(0) AND zero_quotient_w(i);
	END GENERATE loop36;
	loop37 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1533w1577w1578w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1533w1577w(0) AND wire_altsrt_div1_w_rom_dffe_w5c_range1576w(i);
	END GENERATE loop37;
	loop38 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1535w1582w1640w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1535w1582w(0) AND zero_quotient_w(i);
	END GENERATE loop38;
	loop39 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1535w1582w1583w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1535w1582w(0) AND wire_altsrt_div1_w_rom_dffe_w6c_range1581w(i);
	END GENERATE loop39;
	loop40 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1537w1587w1643w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1537w1587w(0) AND zero_quotient_w(i);
	END GENERATE loop40;
	loop41 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1537w1587w1588w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1537w1587w(0) AND wire_altsrt_div1_w_rom_dffe_w7c_range1586w(i);
	END GENERATE loop41;
	loop42 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1539w1592w1646w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1539w1592w(0) AND zero_quotient_w(i);
	END GENERATE loop42;
	loop43 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1539w1592w1593w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1539w1592w(0) AND wire_altsrt_div1_w_rom_dffe_w8c_range1591w(i);
	END GENERATE loop43;
	loop44 : FOR i IN 0 TO 1 GENERATE 
		wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1541w1597w1649w(i) <= wire_altsrt_div1_w_lg_w_rom_mux_w_range1541w1597w(0) AND zero_quotient_w(i)