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SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1529w1567w1631w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1529w1567w1568w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1531w1572w1634w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1531w1572w1573w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1533w1577w1637w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1533w1577w1578w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1535w1582w1640w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1535w1582w1583w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1537w1587w1643w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1537w1587w1588w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1539w1592w1646w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1539w1592w1593w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1541w1597w1649w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1541w1597w1598w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_mux_remainder_w1699w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_mux_remainder_w1703w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_int_w_range969w974w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_int_w_range969w971w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1522w1554w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1522w1621w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1543w1604w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1543w1651w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1545w1609w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1545w1654w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1547w1614w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1547w1657w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1549w1619w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1549w1660w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1525w1559w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1525w1624w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1527w1564w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1527w1627w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1529w1569w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1529w1630w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1531w1574w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1531w1633w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1533w1579w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1533w1636w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1535w1584w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1535w1639w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1537w1589w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1537w1642w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1539w1594w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1539w1645w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1541w1599w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1541w1648w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_mux_remainder_w1700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_int_w_range970w973w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_int_w_range969w976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1522w1552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1543w1602w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1545w1607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1547w1612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1549w1617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1525w1557w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1527w1562w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1529w1567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1531w1572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1533w1577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1535w1582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1537w1587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1539w1592w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_lg_w_rom_mux_w_range1541w1597w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL added_remainder_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL adder_var_dffe_w : STD_LOGIC;
SIGNAL adder_var_int_w : STD_LOGIC;
SIGNAL adder_var_w0c : STD_LOGIC;
SIGNAL adder_var_w10c : STD_LOGIC;
SIGNAL adder_var_w11c : STD_LOGIC;
SIGNAL adder_var_w12c : STD_LOGIC;
SIGNAL adder_var_w1c : STD_LOGIC;
SIGNAL adder_var_w2c : STD_LOGIC;
SIGNAL adder_var_w3c : STD_LOGIC;
SIGNAL adder_var_w4c : STD_LOGIC;
SIGNAL adder_var_w5c : STD_LOGIC;
SIGNAL adder_var_w6c : STD_LOGIC;
SIGNAL adder_var_w7c : STD_LOGIC;
SIGNAL adder_var_w8c : STD_LOGIC;
SIGNAL adder_var_w9c : STD_LOGIC;
SIGNAL clken : STD_LOGIC;
SIGNAL divider_1D_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL divider_2D_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL divider_dffe_1a_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_dffe_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_special_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w0c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w10c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w11c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w12c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w1c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w2c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w3c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w4c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w5c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w6c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w7c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w8c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_next_w9c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w0c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w10c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w11c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w12c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w1c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w2c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w3c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w4c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w5c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w6c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w7c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w8c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_reg_w9c : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_zeros_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL full_neg_rom_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL full_pos_rom_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL mux_remainder_w : STD_LOGIC;
SIGNAL neg_qkd_dffe_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_int_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w0c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w10c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w11c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w12c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w1c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w2c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w3c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w4c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w5c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w6c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w7c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w8c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_reg_w9c : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_rom_w0c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w10c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w11c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w12c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w13c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w1c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w2c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w3c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w4c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w5c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w6c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w7c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w8c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL neg_rom_w9c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL padded_2_zeros_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL padded_3_zeros_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL pos_rom_w0c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w10c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w11c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w12c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w13c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w1c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w2c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w3c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w4c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w5c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w6c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w7c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w8c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pos_rom_w9c : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL Rk_adder_padded_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL Rk_dffe_1a_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL Rk_dffe_2a_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL Rk_next_w0c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w10c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w11c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w12c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w1c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w2c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w3c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w4c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w5c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w6c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w7c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w8c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_next_w9c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w0c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w10c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w11c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w12c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w1c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w2c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w3c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w4c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w5c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w6c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w7c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w8c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_reg_w9c : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_remainder_special_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL Rk_remainder_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL Rk_rom_padded_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL Rk_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL rom_add_w : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL rom_dffe_w0c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w10c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w11c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w12c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w13c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w1c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w2c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w3c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w4c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w5c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w6c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w7c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w8c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_dffe_w9c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_mux_int_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL rom_mux_w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL rom_out_1a_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w0c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w10c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w11c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w12c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w13c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w1c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w2c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w3c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w4c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w5c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w6c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w7c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w8c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_w9c : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL srt_adjust_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL srt_adjusted_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL true_quotient_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL zero_quotient_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_Rk_remainder_special_w_range1698w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w0c_range1551w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w10c_range1601w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w11c_range1606w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w12c_range1611w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w13c_range1616w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w1c_range1556w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w2c_range1561w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w3c_range1566w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w4c_range1571w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w5c_range1576w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w6c_range1581w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w7c_range1586w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w8c_range1591w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_dffe_w9c_range1596w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_mux_int_w_range970w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_mux_int_w_range969w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_mux_w_range1522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_mux_w_range1543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_mux_w_range1545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altsrt_div1_w_rom_mux_w_range1547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
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