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📄 div.vhd

📁 8051的vhdl源代码
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 USE ieee.std_logic_1164.all;

 ENTITY  div_altsrt_div_d4h IS 
	 PORT 
	 ( 
		 aclr	:	IN  STD_LOGIC := '0';
		 clock	:	IN  STD_LOGIC := '0';
		 denom	:	IN  STD_LOGIC_VECTOR (23 DOWNTO 0);
		 divider	:	OUT  STD_LOGIC_VECTOR (23 DOWNTO 0);
		 numer	:	IN  STD_LOGIC_VECTOR (23 DOWNTO 0);
		 quotient	:	OUT  STD_LOGIC_VECTOR (27 DOWNTO 0);
		 remain	:	OUT  STD_LOGIC_VECTOR (23 DOWNTO 0)
	 ); 
 END div_altsrt_div_d4h;

 ARCHITECTURE RTL OF div_altsrt_div_d4h IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 SIGNAL  wire_adder_block21_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block21_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block22_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block22_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block23_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block23_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block24_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block24_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block25_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block25_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block26_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block26_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block27_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block27_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block28_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block28_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block29_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block29_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block30_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block30_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block31_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block31_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_block32_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_block32_Rk_next	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_adder_last_block34_divider_next	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_adder_last_block34_Rk_next	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_altsyncram7_q_a	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL	 adder_var_dffe	:	STD_LOGIC
	 -- synopsys translate_off
	  := '0'
	 -- synopsys translate_on
	 ;
	 SIGNAL	 divider_dffe_1a	:	STD_LOGIC_VECTOR(23 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 divider_dffe_2a	:	STD_LOGIC_VECTOR(23 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 neg_qkd_dffe	:	STD_LOGIC_VECTOR(26 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 Rk_dffe_1a	:	STD_LOGIC_VECTOR(23 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 Rk_dffe_2a	:	STD_LOGIC_VECTOR(23 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 rom_out_2a_dffe	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	 rom_reg_dffe0c	:	STD_LOGIC_VECTOR(77 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe0c_w990w	:	STD_LOGIC_VECTOR (77 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe10c	:	STD_LOGIC_VECTOR(17 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe10c_w1010w	:	STD_LOGIC_VECTOR (17 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe11c	:	STD_LOGIC_VECTOR(11 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe11c_w1012w	:	STD_LOGIC_VECTOR (11 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe12c	:	STD_LOGIC_VECTOR(5 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe12c_w1014w	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe1c	:	STD_LOGIC_VECTOR(71 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe1c_w992w	:	STD_LOGIC_VECTOR (71 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe2c	:	STD_LOGIC_VECTOR(65 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe2c_w994w	:	STD_LOGIC_VECTOR (65 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe3c	:	STD_LOGIC_VECTOR(59 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe3c_w996w	:	STD_LOGIC_VECTOR (59 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe4c	:	STD_LOGIC_VECTOR(53 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe4c_w998w	:	STD_LOGIC_VECTOR (53 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe5c	:	STD_LOGIC_VECTOR(47 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe5c_w1000w	:	STD_LOGIC_VECTOR (47 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe6c	:	STD_LOGIC_VECTOR(41 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe6c_w1002w	:	STD_LOGIC_VECTOR (41 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe7c	:	STD_LOGIC_VECTOR(35 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe7c_w1004w	:	STD_LOGIC_VECTOR (35 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe8c	:	STD_LOGIC_VECTOR(29 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe8c_w1006w	:	STD_LOGIC_VECTOR (29 DOWNTO 0);
	 SIGNAL	 rom_reg_dffe9c	:	STD_LOGIC_VECTOR(23 DOWNTO 0)
	 -- synopsys translate_off
	  := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL  wire_rom_reg_dffe9c_w1008w	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_add_sub35_result	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_add_sub36_result	:	STD_LOGIC_VECTOR (27 DOWNTO 0);
	 SIGNAL  wire_add_sub37_datab	:	STD_LOGIC_VECTOR (27 DOWNTO 0);
	 SIGNAL  wire_add_sub37_result	:	STD_LOGIC_VECTOR (27 DOWNTO 0);
	 SIGNAL  wire_add_sub8_result	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block10_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block10_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block10_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block10_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block10_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block11_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block11_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block11_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block11_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block11_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block12_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block12_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block12_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block12_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block12_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block13_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block13_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block13_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block13_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block13_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block14_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block14_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block14_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block14_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block14_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block15_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block15_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block15_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block15_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block15_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block16_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block16_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block16_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block16_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block16_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block17_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block17_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block17_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block17_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block17_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block18_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block18_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block18_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block18_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block18_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block19_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block19_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block19_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block19_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block19_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block20_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block20_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block20_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block20_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block20_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block33_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block33_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block33_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block33_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block33_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_rom_block9_adder_var	:	STD_LOGIC;
	 SIGNAL  wire_rom_block9_divider_reg	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_rom_block9_neg_qkd_reg	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_rom_block9_Rk_reg	:	STD_LOGIC_VECTOR (24 DOWNTO 0);
	 SIGNAL  wire_rom_block9_rom	:	STD_LOGIC_VECTOR (2 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w980w	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w978w	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w974w975w	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w971w972w	:	STD_LOGIC_VECTOR (26 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_mux_remainder_w1700w1704w	:	STD_LOGIC_VECTOR (27 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_mux_remainder_w1700w1701w	:	STD_LOGIC_VECTOR (23 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w976w979w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_int_w_range969w976w977w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1522w1552w1622w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1522w1552w1553w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1543w1602w1652w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1543w1602w1603w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1545w1607w1655w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1545w1607w1608w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1547w1612w1658w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1547w1612w1613w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1549w1617w1661w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1549w1617w1618w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1525w1557w1625w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1525w1557w1558w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1527w1562w1628w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
	 SIGNAL  wire_altsrt_div1_w_lg_w_lg_w_rom_mux_w_range1527w1562w1563w	:	STD_LOGIC_VECTOR (1 DOWNTO 0);

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