📄 div.vhd
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:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL Rk_dffe_2a : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rom_out_2a_dffe : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_rom_block10_w1739w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL wire_rom_block10_w1737w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1733w1734w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1730w1731w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1735w1738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1735w1736w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rom_block10_w_lg_w_rom_mux_w_range1728w1733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rom_block10_w_lg_w_rom_mux_w_range1728w1730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rom_block10_w_lg_w_rom_mux_w_range1729w1732w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rom_block10_w_lg_w_rom_mux_w_range1728w1735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL adder_var_dffe_w : STD_LOGIC;
SIGNAL adder_var_w : STD_LOGIC;
SIGNAL clken : STD_LOGIC;
SIGNAL divider_1D_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL divider_2D_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL divider_dffe_1a_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_dffe_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_in_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL divider_zeros_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_dffe_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL neg_qkd_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL padded_2_zeros_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL padded_3_zeros_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL Rk_dffe_1a_w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_dffe_2a_w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL Rk_in_w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL rom_add_w : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL rom_mux_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL rom_out_1a_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rom_out_dffe_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_rom_block10_w_rom_mux_w_range1729w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rom_block10_w_rom_mux_w_range1728w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altsyncram
GENERIC
(
ADDRESS_ACLR_A : STRING := "UNUSED";
ADDRESS_ACLR_B : STRING := "NONE";
ADDRESS_REG_B : STRING := "CLOCK1";
BYTE_SIZE : NATURAL := 8;
BYTEENA_ACLR_A : STRING := "UNUSED";
BYTEENA_ACLR_B : STRING := "NONE";
BYTEENA_REG_B : STRING := "CLOCK1";
CLOCK_ENABLE_CORE_A : STRING := "USE_INPUT_CLKEN";
CLOCK_ENABLE_CORE_B : STRING := "USE_INPUT_CLKEN";
CLOCK_ENABLE_INPUT_A : STRING := "NORMAL";
CLOCK_ENABLE_INPUT_B : STRING := "NORMAL";
CLOCK_ENABLE_OUTPUT_A : STRING := "NORMAL";
CLOCK_ENABLE_OUTPUT_B : STRING := "NORMAL";
ENABLE_ECC : STRING := "FALSE";
IMPLEMENT_IN_LES : STRING := "OFF";
INDATA_ACLR_A : STRING := "UNUSED";
INDATA_ACLR_B : STRING := "NONE";
INDATA_REG_B : STRING := "CLOCK1";
INIT_FILE : STRING := "UNUSED";
INIT_FILE_LAYOUT : STRING := "PORT_A";
MAXIMUM_DEPTH : NATURAL := 0;
NUMWORDS_A : NATURAL := 0;
NUMWORDS_B : NATURAL := 0;
OPERATION_MODE : STRING := "BIDIR_DUAL_PORT";
OUTDATA_ACLR_A : STRING := "NONE";
OUTDATA_ACLR_B : STRING := "NONE";
OUTDATA_REG_A : STRING := "UNREGISTERED";
OUTDATA_REG_B : STRING := "UNREGISTERED";
POWER_UP_UNINITIALIZED : STRING := "FALSE";
RAM_BLOCK_TYPE : STRING := "AUTO";
RDCONTROL_ACLR_B : STRING := "NONE";
RDCONTROL_REG_B : STRING := "CLOCK1";
READ_DURING_WRITE_MODE_MIXED_PORTS : STRING := "DONT_CARE";
read_during_write_mode_port_a : STRING := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : STRING := "NEW_DATA_NO_NBE_READ";
WIDTH_A : NATURAL;
WIDTH_B : NATURAL := 1;
WIDTH_BYTEENA_A : NATURAL := 1;
WIDTH_BYTEENA_B : NATURAL := 1;
WIDTHAD_A : NATURAL;
WIDTHAD_B : NATURAL := 1;
WRCONTROL_ACLR_A : STRING := "UNUSED";
WRCONTROL_ACLR_B : STRING := "NONE";
WRCONTROL_WRADDRESS_REG_B : STRING := "CLOCK1";
INTENDED_DEVICE_FAMILY : STRING := "Cyclone II";
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "altsyncram"
);
PORT
(
aclr0 : IN STD_LOGIC := '0';
aclr1 : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR(WIDTHAD_A-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR(WIDTHAD_B-1 DOWNTO 0) := (OTHERS => '1');
addressstall_a : IN STD_LOGIC := '0';
addressstall_b : IN STD_LOGIC := '0';
byteena_a : IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_A-1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_B-1 DOWNTO 0) := (OTHERS => '1');
clock0 : IN STD_LOGIC := '1';
clock1 : IN STD_LOGIC := '1';
clocken0 : IN STD_LOGIC := '1';
clocken1 : IN STD_LOGIC := '1';
clocken2 : IN STD_LOGIC := '1';
clocken3 : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0) := (OTHERS => '1');
data_b : IN STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0) := (OTHERS => '1');
eccstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO 26 GENERATE
wire_rom_block10_w1739w(i) <= wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1735w1738w(0) AND divider_zeros_w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 26 GENERATE
wire_rom_block10_w1737w(i) <= wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1735w1736w(0) AND divider_1D_w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 26 GENERATE
wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1733w1734w(i) <= wire_rom_block10_w_lg_w_rom_mux_w_range1728w1733w(0) AND divider_2D_w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 26 GENERATE
wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1730w1731w(i) <= wire_rom_block10_w_lg_w_rom_mux_w_range1728w1730w(0) AND divider_1D_w(i);
END GENERATE loop3;
wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1735w1738w(0) <= wire_rom_block10_w_lg_w_rom_mux_w_range1728w1735w(0) AND wire_rom_block10_w_lg_w_rom_mux_w_range1729w1732w(0);
wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1735w1736w(0) <= wire_rom_block10_w_lg_w_rom_mux_w_range1728w1735w(0) AND wire_rom_block10_w_rom_mux_w_range1729w(0);
wire_rom_block10_w_lg_w_rom_mux_w_range1728w1733w(0) <= wire_rom_block10_w_rom_mux_w_range1728w(0) AND wire_rom_block10_w_lg_w_rom_mux_w_range1729w1732w(0);
wire_rom_block10_w_lg_w_rom_mux_w_range1728w1730w(0) <= wire_rom_block10_w_rom_mux_w_range1728w(0) AND wire_rom_block10_w_rom_mux_w_range1729w(0);
wire_rom_block10_w_lg_w_rom_mux_w_range1729w1732w(0) <= NOT wire_rom_block10_w_rom_mux_w_range1729w(0);
wire_rom_block10_w_lg_w_rom_mux_w_range1728w1735w(0) <= NOT wire_rom_block10_w_rom_mux_w_range1728w(0);
adder_var <= adder_var_dffe_w;
adder_var_dffe_w <= adder_var_dffe;
adder_var_w <= rom_out_1a_w(2);
clken <= '1';
divider_1D_w <= ( padded_3_zeros_w & divider_dffe_1a_w);
divider_2D_w <= ( padded_2_zeros_w & divider_dffe_1a_w & "0");
divider_dffe_1a_w <= divider_dffe_1a;
divider_dffe_w <= divider_dffe_2a;
divider_in_w <= divider;
divider_reg <= divider_dffe_w;
divider_zeros_w <= "000000000000000000000000000";
neg_qkd_dffe_w <= neg_qkd_dffe;
neg_qkd_reg <= neg_qkd_dffe_w;
neg_qkd_w <= (((wire_rom_block10_w1739w OR wire_rom_block10_w1737w) OR wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1733w1734w) OR wire_rom_block10_w_lg_w_lg_w_rom_mux_w_range1728w1730w1731w);
padded_2_zeros_w <= "00";
padded_3_zeros_w <= "000";
Rk_dffe_1a_w <= Rk_dffe_1a;
Rk_dffe_2a_w <= Rk_dffe_2a;
Rk_in_w <= Rk;
Rk_reg <= Rk_dffe_2a_w;
rom <= rom_out_dffe_w;
rom_add_w <= ( Rk_in_w(24 DOWNTO 17) & divider_in_w(22 DOWNTO 19));
rom_mux_w <= rom_out_1a_w(1 DOWNTO 0);
rom_out_1a_w <= wire_altsyncram40_q_a;
rom_out_dffe_w <= rom_out_2a_dffe;
wire_rom_block10_w_rom_mux_w_range1729w(0) <= rom_mux_w(0);
wire_rom_block10_w_rom_mux_w_range1728w(0) <= rom_mux_w(1);
altsyncram40 : altsyncram
GENERIC MAP (
INIT_FILE => "div.hex",
OPERATION_MODE => "ROM",
WIDTH_A => 3,
WIDTHAD_A => 12,
INTENDED_DEVICE_FAMILY => "Cyclone II"
)
PORT MAP (
address_a => rom_add_w,
clock0 => clock,
clocken0 => clken,
q_a => wire_altsyncram40_q_a
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN adder_var_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN adder_var_dffe <= adder_var_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN divider_dffe_1a <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN divider_dffe_1a <= divider_in_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN divider_dffe_2a <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN divider_dffe_2a <= divider_dffe_1a_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN neg_qkd_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN neg_qkd_dffe <= neg_qkd_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN Rk_dffe_1a <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN Rk_dffe_1a <= Rk_in_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN Rk_dffe_2a <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN Rk_dffe_2a <= Rk_dffe_1a_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rom_out_2a_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN rom_out_2a_dffe <= rom_out_1a_w;
END IF;
END IF;
END PROCESS;
END RTL; --div_rom_block_f8k
LIBRARY altera_mf;
USE altera_mf.all;
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = altsyncram 2 lpm_add_sub 6 reg 802
LIBRARY ieee;
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