pwm_main.map.qmsg

脉冲宽度调制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 10:41:22 2007 " "Info: Processing started: Mon Nov 05 10:41:22 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pwm_main -c pwm_main " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pwm_main -c pwm_main" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm_main.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file pwm_main.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm_main " "Info: Found entity 1: pwm_main" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 altufm_osc0_altufm_osc_1p3 " "Info: Found entity 2: altufm_osc0_altufm_osc_1p3" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 clk_gen " "Info: Found entity 3: clk_gen" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 93 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 duty_cycle " "Info: Found entity 4: duty_cycle" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 117 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 pwm_gen " "Info: Found entity 5: pwm_gen" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 144 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pwm_main " "Info: Elaborating entity \"pwm_main\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altufm_osc0_altufm_osc_1p3 altufm_osc0_altufm_osc_1p3:u1 " "Info: Elaborating entity \"altufm_osc0_altufm_osc_1p3\" for hierarchy \"altufm_osc0_altufm_osc_1p3:u1\"" {  } { { "pwm_main.v" "u1" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 25 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen clk_gen:u2 " "Info: Elaborating entity \"clk_gen\" for hierarchy \"clk_gen:u2\"" {  } { { "pwm_main.v" "u2" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 26 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 pwm_main.v(107) " "Warning (10230): Verilog HDL assignment warning at pwm_main.v(107): truncated value with size 32 to match size of target (19)" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "duty_cycle duty_cycle:u3 " "Info: Elaborating entity \"duty_cycle\" for hierarchy \"duty_cycle:u3\"" {  } { { "pwm_main.v" "u3" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 27 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 pwm_main.v(130) " "Warning (10230): Verilog HDL assignment warning at pwm_main.v(130): truncated value with size 32 to match size of target (4)" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 pwm_main.v(134) " "Warning (10230): Verilog HDL assignment warning at pwm_main.v(134): truncated value with size 32 to match size of target (4)" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_gen pwm_gen:u4 " "Info: Elaborating entity \"pwm_gen\" for hierarchy \"pwm_gen:u4\"" {  } { { "pwm_main.v" "u4" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 28 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 pwm_main.v(162) " "Warning (10230): Verilog HDL assignment warning at pwm_main.v(162): truncated value with size 32 to match size of target (4)" {  } { { "pwm_main.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "63 " "Info: Implemented 63 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "54 " "Info: Implemented 54 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Info: Implemented 1 User Flash Memory blocks" {  } {  } 0 0 "Implemented %1!d! User Flash Memory blocks" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 10:41:25 2007 " "Info: Processing ended: Mon Nov 05 10:41:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}