fir.fit.summary

通过VHDL语言进行数字信号处理的FIR操作

Flow Status : Successful - Wed Mar 05 21:21:58 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : fir
Top-level Entity Name : fir
Family : Cyclone
Device : EP1C3T100C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 728 / 2,910 ( 25 % )
Total pins : 18 / 65 ( 27 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )