📄 fir.fit.rpt
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+------------------------------------+------------------------------+
; 1 Async. clear ; 33 ;
; 1 Clock ; 62 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.14) ; Number of LABs (Total = 88) ;
+---------------------------------------------+------------------------------+
; 0 ; 1 ;
; 1 ; 0 ;
; 2 ; 3 ;
; 3 ; 3 ;
; 4 ; 4 ;
; 5 ; 1 ;
; 6 ; 9 ;
; 7 ; 6 ;
; 8 ; 11 ;
; 9 ; 4 ;
; 10 ; 46 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.11) ; Number of LABs (Total = 88) ;
+-------------------------------------------------+------------------------------+
; 0 ; 1 ;
; 1 ; 5 ;
; 2 ; 3 ;
; 3 ; 0 ;
; 4 ; 3 ;
; 5 ; 3 ;
; 6 ; 22 ;
; 7 ; 8 ;
; 8 ; 14 ;
; 9 ; 2 ;
; 10 ; 27 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 10.94) ; Number of LABs (Total = 88) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 10 ;
; 4 ; 6 ;
; 5 ; 4 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 15 ;
; 10 ; 4 ;
; 11 ; 1 ;
; 12 ; 6 ;
; 13 ; 7 ;
; 14 ; 4 ;
; 15 ; 6 ;
; 16 ; 4 ;
; 17 ; 3 ;
; 18 ; 13 ;
; 19 ; 1 ;
+----------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Mar 05 21:21:35 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fir -c fir
Info: Selected device EP1C3T100C6 for design "fir"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: No exact pin location assignment(s) for 18 pins of 18 total pins
Info: Pin Dout[7] not assigned to an exact location on the device
Info: Pin Dout[6] not assigned to an exact location on the device
Info: Pin Dout[5] not assigned to an exact location on the device
Info: Pin Dout[4] not assigned to an exact location on the device
Info: Pin Dout[3] not assigned to an exact location on the device
Info: Pin Dout[2] not assigned to an exact location on the device
Info: Pin Dout[1] not assigned to an exact location on the device
Info: Pin Dout[0] not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin clear not assigned to an exact location on the device
Info: Pin Din[7] not assigned to an exact location on the device
Info: Pin Din[6] not assigned to an exact location on the device
Info: Pin Din[5] not assigned to an exact location on the device
Info: Pin Din[4] not assigned to an exact location on the device
Info: Pin Din[3] not assigned to an exact location on the device
Info: Pin Din[2] not assigned to an exact location on the device
Info: Pin Din[1] not assigned to an exact location on the device
Info: Pin Din[0] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "clk" to use Global clock in PIN 10
Info: Automatically promoted signal "clear" to use Global clock in PIN 66
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 8 input, 8 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used -- 11 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 16 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 7.928 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y13; Fanout = 26; REG Node = 'dff89:inst34|Dout[1]'
Info: 2: + IC(0.648 ns) + CELL(0.333 ns) = 0.981 ns; Loc. = LAB_X9_Y13; Fanout = 2; COMB Node = 'mult242:inst40|add~2106COUT1_2185'
Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.043 ns; Loc. = LAB_X9_Y13; Fanout = 2; COMB Node = 'mult242:inst40|add~2075COUT1_2187'
Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.105 ns; Loc. = LAB_X9_Y13; Fanout = 2; COMB Node = 'mult242:inst40|add~2044COUT1_2189'
Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 1.167 ns; Loc. = LAB_X9_Y13; Fanout = 2; COMB Node = 'mult242:inst40|add~2034COUT1_2191'
Info: 6: + IC(0.000 ns) + CELL(0.199 ns) = 1.366 ns; Loc. = LAB_X9_Y13; Fanout = 5; COMB Node = 'mult242:inst40|add~2024'
Info: 7: + IC(0.000 ns) + CELL(0.523 ns) = 1.889 ns; Loc. = LAB_X9_Y13⌨️ 快捷键说明
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