testlatch.hier_info

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。

|testlatch
GREEN_LED <= JTAGcore:inst4.GREEN_LED
N_PWREN => JTAGcore:inst4.RESET
N_TXE => JTAGcore:inst4.N_TXE
N_RXF => JTAGcore:inst4.N_RXF
CLK => JTAGcore:inst4.CLK
CDONE => JTAGcore:inst4.CDONE
DATAOUT => JTAGcore:inst4.DATAOUT
D[0] <= JTAGcore:inst4.d[0]
D[1] <= JTAGcore:inst4.d[1]
D[2] <= JTAGcore:inst4.d[2]
D[3] <= JTAGcore:inst4.d[3]
D[4] <= JTAGcore:inst4.d[4]
D[5] <= JTAGcore:inst4.d[5]
D[6] <= JTAGcore:inst4.d[6]
D[7] <= JTAGcore:inst4.d[7]
N_RD <= JTAGcore:inst4.N_RD
RED_LED <= JTAGcore:inst4.RED_LED
N_CE <= JTAGcore:inst4.N_CE
N_CONF <= JTAGcore:inst4.N_CONF
WR <= JTAGcore:inst4.WR
ASDI <= JTAGcore:inst4.ASDI
N_CS <= JTAGcore:inst4.N_CS
JTCK <= JTAGcore:inst4.JTCK
pin_44_OUT <= inst.DB_MAX_OUTPUT_PORT_TYPE
CFG0 => inst.IN0
CFG2 => inst.IN1
CFG1 => inst.IN2
CFG3 => inst.IN3


|testlatch|JTAGcore:inst4
GREEN_LED <= GREEN_LED~0.DB_MAX_OUTPUT_PORT_TYPE
RED_LED <= RED_LED~reg0.DB_MAX_OUTPUT_PORT_TYPE
N_RD <= N_RD~0.DB_MAX_OUTPUT_PORT_TYPE
WR <= WR~reg0.DB_MAX_OUTPUT_PORT_TYPE
JTCK <= JTCK~0.DB_MAX_OUTPUT_PORT_TYPE
N_CONF <= N_CONF~reg0.DB_MAX_OUTPUT_PORT_TYPE
N_CS <= N_CS~reg0.DB_MAX_OUTPUT_PORT_TYPE
N_CE <= N_CE~reg0.DB_MAX_OUTPUT_PORT_TYPE
ASDI <= ASDI~0.DB_MAX_OUTPUT_PORT_TYPE
CDONE => CDONE~0.IN1
DATAOUT => To_FT245[1].DATAB
d[0] <= shiftout:shifter.port4
d[0] <= d~15
d[1] <= shiftout:shifter.port4
d[1] <= d~14
d[2] <= shiftout:shifter.port4
d[2] <= d~13
d[3] <= shiftout:shifter.port4
d[3] <= d~12
d[4] <= shiftout:shifter.port4
d[4] <= d~11
d[5] <= shiftout:shifter.port4
d[5] <= d~10
d[6] <= shiftout:shifter.port4
d[6] <= d~9
d[7] <= shiftout:shifter.port4
d[7] <= d~8
CLK => CLK~0.IN1
N_RXF => RXF.IN0
N_TXE => TXE.IN0
RESET => RESET~0.IN1


|testlatch|JTAGcore:inst4|shiftout:shifter
dout[0] <= shifter[0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= shifter[1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= shifter[2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= shifter[3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= shifter[4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= shifter[5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= shifter[6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= shifter[7].DB_MAX_OUTPUT_PORT_TYPE
so <= shifter[0].DB_MAX_OUTPUT_PORT_TYPE
rdy <= rdy~reg0.DB_MAX_OUTPUT_PORT_TYPE
T_CLK <= T_CLK~reg0.DB_MAX_OUTPUT_PORT_TYPE
din[0] => shifter~15.DATAB
din[1] => shifter~14.DATAB
din[2] => shifter~13.DATAB
din[3] => shifter~12.DATAB
din[4] => shifter~11.DATAB
din[5] => shifter~10.DATAB
din[6] => shifter~9.DATAB
din[7] => shifter~8.DATAB
si => shifter~0.DATAB
load => always0~1.IN1
reset => bitcount~16.OUTPUTSELECT
reset => bitcount~17.OUTPUTSELECT
reset => bitcount~18.OUTPUTSELECT
reset => bitcount~19.OUTPUTSELECT
reset => T_CLK~4.OUTPUTSELECT
reset => rdy~4.OUTPUTSELECT
reset => shifter~24.OUTPUTSELECT
reset => shifter~25.OUTPUTSELECT
reset => shifter~26.OUTPUTSELECT
reset => shifter~27.OUTPUTSELECT
reset => shifter~28.OUTPUTSELECT
reset => shifter~29.OUTPUTSELECT
reset => shifter~30.OUTPUTSELECT
reset => shifter~31.OUTPUTSELECT
clk => bitcount[2].CLK
clk => bitcount[1].CLK
clk => bitcount[0].CLK
clk => T_CLK~reg0.CLK
clk => rdy~reg0.CLK
clk => shifter[7].CLK
clk => shifter[6].CLK
clk => shifter[5].CLK
clk => shifter[4].CLK
clk => shifter[3].CLK
clk => shifter[2].CLK
clk => shifter[1].CLK
clk => shifter[0].CLK
clk => bitcount[3].CLK