shift.map.qmsg

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 27 17:38:03 2005 " "Info: Processing started: Tue Dec 27 17:38:03 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off shift -c shift " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off shift -c shift" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shift.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift " "Info: Found entity 1: shift" {  } { { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shiftout.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shiftout.v" { { "Info" "ISGN_ENTITY_NAME" "1 shiftout " "Info: Found entity 1: shiftout" {  } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 7 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 shiftout.v(48) " "Warning: Verilog HDL assignment warning at shiftout.v(48): truncated value with size 32 to match size of target (4)" {  } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 48 0 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "38 " "Info: Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "15 " "Info: Implemented 15 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 27 17:38:04 2005 " "Info: Processing ended: Tue Dec 27 17:38:04 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}