fenping5.vhd

数字波形存储器VHDL源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenping5 is
   port(clk_4m:in std_logic;
         clk8,clk9:out std_logic);

end;
architecture art of  fenping5 is
signal  cp8 ,cp9 :std_logic;
signal count:std_logic_vector(15 downto 0);
signal s: std_logic_vector(15 downto 0);

      begin
 process(clk_4m) is
       begin
          if(clk_4m'event and clk_4m='1') then
                if count="0000001000000000" then
                  count<=(others=>'0');cp8<=not cp8;
                else count<=count+1;
          end if;
        end if;
        clk8<=cp8;
  end process;
process(cp8) is
        begin
        if(cp8'event and cp8='1') then
                if s="0000000000000010" then
                 s<=(others=>'0');cp9<=not cp9;
                else s<=s+1;
          end if;
        end if;
            clk9<=cp9;
        end process;
       
end;