mult_add_k512.tdf

数字波形存储器VHDL源码

--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1=CLOCK0 ADDNSUB_MULTIPLIER_REGISTER1=CLOCK0 DEDICATED_MULTIPLIER_CIRCUITRY=AUTO DEVICE_FAMILY=ACEX1K DSP_BLOCK_BALANCING=Auto INPUT_REGISTER_A0=CLOCK0 INPUT_REGISTER_B0=CLOCK0 INPUT_SOURCE_A0=DATAA INPUT_SOURCE_B0=DATAB INTENDED_DEVICE_FAMILY=Stratix MULTIPLIER1_DIRECTION=ADD MULTIPLIER_REGISTER0=CLOCK0 NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER=CLOCK0 REPRESENTATION_A=UNSIGNED REPRESENTATION_B=UNSIGNED SIGNED_PIPELINE_REGISTER_A=CLOCK0 SIGNED_PIPELINE_REGISTER_B=CLOCK0 SIGNED_REGISTER_A=CLOCK0 SIGNED_REGISTER_B=CLOCK0 WIDTH_A=11 WIDTH_B=8 WIDTH_RESULT=11 clock0 dataa datab result CARRY_CHAIN=MANUAL CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 4.0 cbx_altmult_add 2004:01:19:10:20:18:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratix 2004:02:27:16:26:40:SJ  VERSION_END


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include "alt_mac_mult.inc";
include "alt_mac_out.inc";

--synthesis_resources = alt_mac_mult 1 alt_mac_out 1 
SUBDESIGN mult_add_k512
( 
	clock0	:	input;
	dataa[10..0]	:	input;
	datab[7..0]	:	input;
	result[10..0]	:	output;
) 
VARIABLE 
	mac_mult1 : alt_mac_mult
		WITH (
			DATAA_CLEAR = "A_3",
			DATAA_CLOCK = "A_0",
			DATAA_WIDTH = 11,
			DATAB_CLEAR = "A_3",
			DATAB_CLOCK = "A_0",
			DATAB_WIDTH = 8,
			OUTPUT_CLEAR = "A_3",
			OUTPUT_CLOCK = "A_0",
			OUTPUT_WIDTH = 19
		);
	mac_out2 : alt_mac_out
		WITH (
			DATAA_WIDTH = 19,
			OPERATION_MODE = "OUTPUT_ONLY",
			OUTPUT_CLEAR = "A_3",
			OUTPUT_CLOCK = "A_0",
			OUTPUT_WIDTH = 19
		);
	aclr0	: NODE;
	aclr1	: NODE;
	aclr2	: NODE;
	aclr3	: NODE;
	clock1	: NODE;
	clock2	: NODE;
	clock3	: NODE;
	dataa_bus[10..0]	: WIRE;
	datab_bus[7..0]	: WIRE;
	ena0	: NODE;
	ena1	: NODE;
	ena2	: NODE;
	ena3	: NODE;

BEGIN 
	mac_mult1.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult1.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult1.dataa[] = ( dataa_bus[10..0]);
	mac_mult1.datab[] = ( datab_bus[7..0]);
	mac_mult1.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_out2.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_out2.clk[] = ( clock3, clock2, clock1, clock0);
	mac_out2.dataa[] = ( mac_mult1.dataout[18..0]);
	mac_out2.ena[] = ( ena3, ena2, ena1, ena0);
	mac_out2.signa = B"0";
	mac_out2.signb = B"0";
	aclr0 = GND;
	aclr1 = GND;
	aclr2 = GND;
	aclr3 = GND;
	clock1 = VCC;
	clock2 = VCC;
	clock3 = VCC;
	dataa_bus[] = ( dataa[10..0]);
	datab_bus[] = ( datab[7..0]);
	ena0 = VCC;
	ena1 = VCC;
	ena2 = VCC;
	ena3 = VCC;
	result[10..0] = mac_out2.dataout[10..0];
END;
--VALID FILE