boxingcunchu_hier_info

数字波形存储器VHDL源码

|boxingcunchu
ad/cs <= s.DB_MAX_OUTPUT_PORT_TYPE
clk_4m => xuanzhe:inst8.clk
clk_4m => fenpingqi:inst.clk_4m
ALE => control:inst6.ale
WR => control:inst6.wr
a[0] => control:inst6.a[0]
a[1] => control:inst6.a[1]
a[2] => control:inst6.a[2]
a[3] => control:inst6.a[3]
P0[0] => control:inst6.p0[0]
P0[1] => control:inst6.p0[1]
P0[2] => control:inst6.p0[2]
P0[3] => control:inst6.p0[3]
P0[4] => control:inst6.p0[4]
P0[5] => control:inst6.p0[5]
P0[6] => control:inst6.p0[6]
P0[7] => control:inst6.p0[7]
dataout[0] <= lpm_ram_dp0:inst3.q[0]
dataout[1] <= lpm_ram_dp0:inst3.q[1]
dataout[2] <= lpm_ram_dp0:inst3.q[2]
dataout[3] <= lpm_ram_dp0:inst3.q[3]
dataout[4] <= lpm_ram_dp0:inst3.q[4]
dataout[5] <= lpm_ram_dp0:inst3.q[5]
dataout[6] <= lpm_ram_dp0:inst3.q[6]
dataout[7] <= lpm_ram_dp0:inst3.q[7]


|boxingcunchu|xuanzhe:inst8
clk => clkout~reg0.CLK
sel[0] => i~0.IN3
sel[1] => i~0.IN2
sel[2] => i~0.IN1
sel[3] => i~0.IN0
in0 => i~0.IN4
in1 => i~0.IN5
in2 => i~0.IN6
in3 => i~0.IN7
in4 => i~0.IN8
in5 => i~0.IN9
in6 => i~0.IN10
in7 => i~0.IN11
in8 => i~0.IN12
in9 => i~0.IN13
in10 => i~0.IN14
in10 => i~0.IN15
in12 => i~0.IN16
in13 => i~0.IN17
in14 => i~0.IN18
in15 => i~0.IN19
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|fenpingqi:inst
clk_4m => fenping1:b2v_inst8.clk_4m
clk_4m => fenping8:b2v_inst7.clk_4m
clk_4m => fenping7:b2v_inst6.clk_4m
clk_4m => fenping6:b2v_inst5.clk_4m
clk_4m => fenping5:b2v_inst4.clk_4m
clk_4m => fenping4:b2v_inst3.clk_4m
clk_4m => fenping3:b2v_inst2.clk_4m
clk_4m => fenping2:b2v_inst1.clk_4m
clk0 <= fenping1:b2v_inst8.clk0
clk1 <= fenping1:b2v_inst8.clk1
clk2 <= fenping2:b2v_inst1.clk2
clk3 <= fenping2:b2v_inst1.clk3
clk4 <= fenping3:b2v_inst2.clk4
clk5 <= fenping3:b2v_inst2.clk5
clk6 <= fenping4:b2v_inst3.clk6
clk7 <= fenping4:b2v_inst3.clk7
clk8 <= fenping5:b2v_inst4.clk8
clk9 <= fenping5:b2v_inst4.clk9
clk10 <= fenping6:b2v_inst5.clk10
clk11 <= fenping6:b2v_inst5.clk11
clk13 <= fenping7:b2v_inst6.clk13
clk14 <= fenping8:b2v_inst7.clk14
clk15 <= fenping8:b2v_inst7.clk15
clk12 <= fenping7:b2v_inst6.clk12


|boxingcunchu|fenpingqi:inst|fenping2:b2v_inst1
clk_4m => count[14].CLK
clk_4m => count[13].CLK
clk_4m => count[12].CLK
clk_4m => count[11].CLK
clk_4m => count[10].CLK
clk_4m => count[9].CLK
clk_4m => count[8].CLK
clk_4m => count[7].CLK
clk_4m => count[6].CLK
clk_4m => count[5].CLK
clk_4m => count[4].CLK
clk_4m => count[3].CLK
clk_4m => count[2].CLK
clk_4m => count[1].CLK
clk_4m => count[0].CLK
clk_4m => cp2.CLK
clk_4m => count[15].CLK
clk2 <= cp2.DB_MAX_OUTPUT_PORT_TYPE
clk3 <= cp3.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|fenpingqi:inst|fenping3:b2v_inst2
clk_4m => count[14].CLK
clk_4m => count[13].CLK
clk_4m => count[12].CLK
clk_4m => count[11].CLK
clk_4m => count[10].CLK
clk_4m => count[9].CLK
clk_4m => count[8].CLK
clk_4m => count[7].CLK
clk_4m => count[6].CLK
clk_4m => count[5].CLK
clk_4m => count[4].CLK
clk_4m => count[3].CLK
clk_4m => count[2].CLK
clk_4m => count[1].CLK
clk_4m => count[0].CLK
clk_4m => cp4.CLK
clk_4m => count[15].CLK
clk4 <= cp4.DB_MAX_OUTPUT_PORT_TYPE
clk5 <= cp5.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|fenpingqi:inst|fenping4:b2v_inst3
clk_4m => count[14].CLK
clk_4m => count[13].CLK
clk_4m => count[12].CLK
clk_4m => count[11].CLK
clk_4m => count[10].CLK
clk_4m => count[9].CLK
clk_4m => count[8].CLK
clk_4m => count[7].CLK
clk_4m => count[6].CLK
clk_4m => count[5].CLK
clk_4m => count[4].CLK
clk_4m => count[3].CLK
clk_4m => count[2].CLK
clk_4m => count[1].CLK
clk_4m => count[0].CLK
clk_4m => cp6.CLK
clk_4m => count[15].CLK
clk6 <= cp6.DB_MAX_OUTPUT_PORT_TYPE
clk7 <= cp7.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|fenpingqi:inst|fenping5:b2v_inst4
clk_4m => count[14].CLK
clk_4m => count[13].CLK
clk_4m => count[12].CLK
clk_4m => count[11].CLK
clk_4m => count[10].CLK
clk_4m => count[9].CLK
clk_4m => count[8].CLK
clk_4m => count[7].CLK
clk_4m => count[6].CLK
clk_4m => count[5].CLK
clk_4m => count[4].CLK
clk_4m => count[3].CLK
clk_4m => count[2].CLK
clk_4m => count[1].CLK
clk_4m => count[0].CLK
clk_4m => cp8.CLK
clk_4m => count[15].CLK
clk8 <= cp8.DB_MAX_OUTPUT_PORT_TYPE
clk9 <= cp9.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|fenpingqi:inst|fenping6:b2v_inst5
clk_4m => count[14].CLK
clk_4m => count[13].CLK
clk_4m => count[12].CLK
clk_4m => count[11].CLK
clk_4m => count[10].CLK
clk_4m => count[9].CLK
clk_4m => count[8].CLK
clk_4m => count[7].CLK
clk_4m => count[6].CLK
clk_4m => count[5].CLK
clk_4m => count[4].CLK
clk_4m => count[3].CLK
clk_4m => count[2].CLK
clk_4m => count[1].CLK
clk_4m => count[0].CLK
clk_4m => cp10.CLK
clk_4m => count[15].CLK
clk10 <= cp10.DB_MAX_OUTPUT_PORT_TYPE
clk11 <= cp11.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|fenpingqi:inst|fenping7:b2v_inst6
clk_4m => s[14].CLK
clk_4m => s[13].CLK
clk_4m => s[12].CLK
clk_4m => s[11].CLK
clk_4m => s[10].CLK
clk_4m => s[9].CLK
clk_4m => s[8].CLK
clk_4m => s[7].CLK
clk_4m => s[6].CLK
clk_4m => s[5].CLK
clk_4m => s[4].CLK
clk_4m => s[3].CLK
clk_4m => s[2].CLK
clk_4m => s[1].CLK
clk_4m => s[0].CLK
clk_4m => cp12.CLK
clk_4m => s[15].CLK
clk12 <= cp12.DB_MAX_OUTPUT_PORT_TYPE
clk13 <= cp13.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|fenpingqi:inst|fenping8:b2v_inst7
clk_4m => count[14].CLK
clk_4m => count[13].CLK
clk_4m => count[12].CLK
clk_4m => count[11].CLK
clk_4m => count[10].CLK
clk_4m => count[9].CLK
clk_4m => count[8].CLK
clk_4m => count[7].CLK
clk_4m => count[6].CLK
clk_4m => count[5].CLK
clk_4m => count[4].CLK
clk_4m => count[3].CLK
clk_4m => count[2].CLK
clk_4m => count[1].CLK
clk_4m => count[0].CLK
clk_4m => cp14.CLK
clk_4m => count[15].CLK
clk14 <= cp14.DB_MAX_OUTPUT_PORT_TYPE
clk15 <= cp15.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|fenpingqi:inst|fenping1:b2v_inst8
clk_4m => count[14].CLK
clk_4m => count[13].CLK
clk_4m => count[12].CLK
clk_4m => count[11].CLK
clk_4m => count[10].CLK
clk_4m => count[9].CLK
clk_4m => count[8].CLK
clk_4m => count[7].CLK
clk_4m => count[6].CLK
clk_4m => count[5].CLK
clk_4m => count[4].CLK
clk_4m => count[3].CLK
clk_4m => count[2].CLK
clk_4m => count[1].CLK
clk_4m => count[0].CLK
clk_4m => cp0.CLK
clk_4m => count[15].CLK
clk0 <= cp0.DB_MAX_OUTPUT_PORT_TYPE
clk1 <= cp1.DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|control:inst6
p0[0] => data[0].DATAIN
p0[1] => data[1].DATAIN
p0[2] => data[2].DATAIN
p0[3] => data[3].DATAIN
p0[4] => data[4].DATAIN
p0[5] => data[5].DATAIN
p0[6] => data[6].DATAIN
p0[7] => data[7].DATAIN
ale => data[6].CLK
ale => data[5].CLK
ale => data[4].CLK
ale => data[3].CLK
ale => data[2].CLK
ale => data[1].CLK
ale => data[0].CLK
ale => data[7].CLK
wr => s[2].CLK
wr => s[1].CLK
wr => s[0].CLK
wr => s[3].CLK
a[0] => s[0].DATAIN
a[1] => s[1].DATAIN
a[2] => s[2].DATAIN
a[3] => s[3].DATAIN
sel[0] <= s[0].DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= s[1].DB_MAX_OUTPUT_PORT_TYPE
sel[2] <= s[2].DB_MAX_OUTPUT_PORT_TYPE
sel[3] <= s[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE


|boxingcunchu|lpm_ram_dp0:inst3
data[0] => lpm_ram_dp:lpm_ram_dp_component.data[0]
data[1] => lpm_ram_dp:lpm_ram_dp_component.data[1]
data[2] => lpm_ram_dp:lpm_ram_dp_component.data[2]
data[3] => lpm_ram_dp:lpm_ram_dp_component.data[3]
data[4] => lpm_ram_dp:lpm_ram_dp_component.data[4]
data[5] => lpm_ram_dp:lpm_ram_dp_component.data[5]
data[6] => lpm_ram_dp:lpm_ram_dp_component.data[6]
data[7] => lpm_ram_dp:lpm_ram_dp_component.data[7]
wraddress[0] => lpm_ram_dp:lpm_ram_dp_component.wraddress[0]
wraddress[1] => lpm_ram_dp:lpm_ram_dp_component.wraddress[1]
wraddress[2] => lpm_ram_dp:lpm_ram_dp_component.wraddress[2]
wraddress[3] => lpm_ram_dp:lpm_ram_dp_component.wraddress[3]
wraddress[4] => lpm_ram_dp:lpm_ram_dp_component.wraddress[4]
wraddress[5] => lpm_ram_dp:lpm_ram_dp_component.wraddress[5]
wraddress[6] => lpm_ram_dp:lpm_ram_dp_component.wraddress[6]
wraddress[7] => lpm_ram_dp:lpm_ram_dp_component.wraddress[7]
wraddress[8] => lpm_ram_dp:lpm_ram_dp_component.wraddress[8]
wraddress[9] => lpm_ram_dp:lpm_ram_dp_component.wraddress[9]
wraddress[10] => lpm_ram_dp:lpm_ram_dp_component.wraddress[10]
rdaddress[0] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[0]
rdaddress[1] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[1]
rdaddress[2] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[2]
rdaddress[3] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[3]
rdaddress[4] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[4]
rdaddress[5] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[5]
rdaddress[6] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[6]
rdaddress[7] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[7]
rdaddress[8] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[8]
rdaddress[9] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[9]
rdaddress[10] => lpm_ram_dp:lpm_ram_dp_component.rdaddress[10]
wren => lpm_ram_dp:lpm_ram_dp_component.wren
wrclock => lpm_ram_dp:lpm_ram_dp_component.wrclock
rdclock => lpm_ram_dp:lpm_ram_dp_component.rdclock
q[0] <= lpm_ram_dp:lpm_ram_dp_component.q[0]
q[1] <= lpm_ram_dp:lpm_ram_dp_component.q[1]
q[2] <= lpm_ram_dp:lpm_ram_dp_component.q[2]
q[3] <= lpm_ram_dp:lpm_ram_dp_component.q[3]
q[4] <= lpm_ram_dp:lpm_ram_dp_component.q[4]
q[5] <= lpm_ram_dp:lpm_ram_dp_component.q[5]
q[6] <= lpm_ram_dp:lpm_ram_dp_component.q[6]
q[7] <= lpm_ram_dp:lpm_ram_dp_component.q[7]


|boxingcunchu|lpm_ram_dp0:inst3|lpm_ram_dp:lpm_ram_dp_component
data[0] => altdpram:sram.data[0]
data[1] => altdpram:sram.data[1]
data[2] => altdpram:sram.data[2]
data[3] => altdpram:sram.data[3]
data[4] => altdpram:sram.data[4]
data[5] => altdpram:sram.data[5]
data[6] => altdpram:sram.data[6]
data[7] => altdpram:sram.data[7]
rdaddress[0] => altdpram:sram.rdaddress[0]
rdaddress[1] => altdpram:sram.rdaddress[1]
rdaddress[2] => altdpram:sram.rdaddress[2]
rdaddress[3] => altdpram:sram.rdaddress[3]
rdaddress[4] => altdpram:sram.rdaddress[4]
rdaddress[5] => altdpram:sram.rdaddress[5]
rdaddress[6] => altdpram:sram.rdaddress[6]
rdaddress[7] => altdpram:sram.rdaddress[7]
rdaddress[8] => altdpram:sram.rdaddress[8]
rdaddress[9] => altdpram:sram.rdaddress[9]
rdaddress[10] => altdpram:sram.rdaddress[10]
wraddress[0] => altdpram:sram.wraddress[0]
wraddress[1] => altdpram:sram.wraddress[1]
wraddress[2] => altdpram:sram.wraddress[2]
wraddress[3] => altdpram:sram.wraddress[3]
wraddress[4] => altdpram:sram.wraddress[4]
wraddress[5] => altdpram:sram.wraddress[5]
wraddress[6] => altdpram:sram.wraddress[6]
wraddress[7] => altdpram:sram.wraddress[7]
wraddress[8] => altdpram:sram.wraddress[8]
wraddress[9] => altdpram:sram.wraddress[9]
wraddress[10] => altdpram:sram.wraddress[10]
rdclock => altdpram:sram.outclock
wrclock => altdpram:sram.inclock
wren => altdpram:sram.wren
q[0] <= altdpram:sram.q[0]
q[1] <= altdpram:sram.q[1]
q[2] <= altdpram:sram.q[2]
q[3] <= altdpram:sram.q[3]
q[4] <= altdpram:sram.q[4]
q[5] <= altdpram:sram.q[5]
q[6] <= altdpram:sram.q[6]
q[7] <= altdpram:sram.q[7]


|boxingcunchu|lpm_ram_dp0:inst3|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram
wren => segment[0][7].WE
wren => segment[0][6].WE
wren => segment[0][5].WE
wren => segment[0][4].WE
wren => segment[0][3].WE
wren => segment[0][2].WE
wren => segment[0][1].WE
wren => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[0][7].DATAIN
wraddress[0] => segment[0][7].WADDR
wraddress[0] => segment[0][6].WADDR
wraddress[0] => segment[0][5].WADDR
wraddress[0] => segment[0][4].WADDR
wraddress[0] => segment[0][3].WADDR
wraddress[0] => segment[0][2].WADDR
wraddress[0] => segment[0][1].WADDR
wraddress[0] => segment[0][0].WADDR
wraddress[1] => segment[0][7].WADDR1
wraddress[1] => segment[0][6].WADDR1
wraddress[1] => segment[0][5].WADDR1
wraddress[1] => segment[0][4].WADDR1
wraddress[1] => segment[0][3].WADDR1
wraddress[1] => segment[0][2].WADDR1
wraddress[1] => segment[0][1].WADDR1
wraddress[1] => segment[0][0].WADDR1
wraddress[2] => segment[0][7].WADDR2
wraddress[2] => segment[0][6].WADDR2
wraddress[2] => segment[0][5].WADDR2
wraddress[2] => segment[0][4].WADDR2
wraddress[2] => segment[0][3].WADDR2
wraddress[2] => segment[0][2].WADDR2
wraddress[2] => segment[0][1].WADDR2
wraddress[2] => segment[0][0].WADDR2
wraddress[3] => segment[0][7].WADDR3
wraddress[3] => segment[0][6].WADDR3
wraddress[3] => segment[0][5].WADDR3
wraddress[3] => segment[0][4].WADDR3
wraddress[3] => segment[0][3].WADDR3
wraddress[3] => segment[0][2].WADDR3
wraddress[3] => segment[0][1].WADDR3
wraddress[3] => segment[0][0].WADDR3
wraddress[4] => segment[0][7].WADDR4
wraddress[4] => segment[0][6].WADDR4
wraddress[4] => segment[0][5].WADDR4
wraddress[4] => segment[0][4].WADDR4
wraddress[4] => segment[0][3].WADDR4
wraddress[4] => segment[0][2].WADDR4
wraddress[4] => segment[0][1].WADDR4