boxingcunchu.csf.qmsg

数字波形存储器VHDL源码

{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 04 09:41:18 2005 " "Info: Processing started: Thu Aug 04 09:41:18 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off boxingcunchu -c boxingcunchu " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off boxingcunchu -c boxingcunchu" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 04 09:41:22 2005 " "Info: Processing ended: Thu Aug 04 09:41:22 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 04 09:41:24 2005 " "Info: Processing started: Thu Aug 04 09:41:24 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off boxingcunchu -c boxingcunchu " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off boxingcunchu -c boxingcunchu" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk_4m " "Info: Assuming node clk_4m is an undefined clock" {  } { { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 120 -328 -160 136 "clk_4m" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_4m" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "WR " "Info: Assuming node WR is an undefined clock" {  } { { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { -8 -328 -160 8 "WR" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node ALE is an undefined clock" {  } { { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 8 -328 -160 24 "ALE" "" } } } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0}  } {  } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_RIPPLE_CLK" "fenpingqi:inst\|fenping1:b2v_inst8\|cp0 " "Info: Detected ripple clock fenpingqi:inst\|fenping1:b2v_inst8\|cp0 as buffer" {  } { { "D:/xiongxusheng/eda/boxingcunchu/fenping1.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping1.vhd" 17 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpingqi:inst\|fenping1:b2v_inst8\|cp0" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "fenpingqi:inst\|fenping2:b2v_inst1\|cp2 " "Info: Detected ripple clock fenpingqi:inst\|fenping2:b2v_inst1\|cp2 as buffer" {  } { { "D:/xiongxusheng/eda/boxingcunchu/fenping2.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping2.vhd" 17 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpingqi:inst\|fenping2:b2v_inst1\|cp2" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "fenpingqi:inst\|fenping4:b2v_inst3\|cp6 " "Info: Detected ripple clock fenpingqi:inst\|fenping4:b2v_inst3\|cp6 as buffer" {  } { { "D:/xiongxusheng/eda/boxingcunchu/fenping4.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping4.vhd" 17 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpingqi:inst\|fenping4:b2v_inst3\|cp6" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "fenpingqi:inst\|fenping5:b2v_inst4\|cp8 " "Info: Detected ripple clock fenpingqi:inst\|fenping5:b2v_inst4\|cp8 as buffer" {  } { { "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" 17 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpingqi:inst\|fenping5:b2v_inst4\|cp8" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "fenpingqi:inst\|fenping7:b2v_inst6\|cp12 " "Info: Detected ripple clock fenpingqi:inst\|fenping7:b2v_inst6\|cp12 as buffer" {  } { { "D:/xiongxusheng/eda/boxingcunchu/fenping7.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping7.vhd" 17 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpingqi:inst\|fenping7:b2v_inst6\|cp12" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "fenpingqi:inst\|fenping8:b2v_inst7\|cp14 " "Info: Detected ripple clock fenpingqi:inst\|fenping8:b2v_inst7\|cp14 as buffer" {  } { { "D:/xiongxusheng/eda/boxingcunchu/finping8.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/finping8.vhd" 17 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpingqi:inst\|fenping8:b2v_inst7\|cp14" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "fenpingqi:inst\|fenping3:b2v_inst2\|cp4 " "Info: Detected ripple clock fenpingqi:inst\|fenping3:b2v_inst2\|cp4 as buffer" {  } { { "D:/xiongxusheng/eda/boxingcunchu/fenping3.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping3.vhd" 17 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpingqi:inst\|fenping3:b2v_inst2\|cp4" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "fenpingqi:inst\|fenping3:b2v_inst2\|cp5 " "Info: Detected ripple clock fenpingqi:inst\|fenping3:b2v_inst2\|cp5 as buffer" {  } { { "D:/xiongxusheng/eda/boxingcunchu/fenping3.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping3.vhd" 27 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpingqi:inst\|fenping3:b2v_inst2\|cp5" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "xuanzhe:inst8\|clkout~reg0 " "Info: Detected ripple clock xuanzhe:inst8\|clkout~reg0 as buffer" {  } { { "D:/xiongxusheng/eda/xuanzhe.vhd" "" "" { Text "D:/xiongxusheng/eda/xuanzhe.vhd" 16 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "xuanzhe:inst8\|clkout~reg0" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_4m register fenpingqi:inst\|fenping5:b2v_inst4\|lpm_counter:s_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\] register fenpingqi:inst\|fenping5:b2v_inst4\|cp9 81.97 MHz 12.2 ns Internal " "Info: Clock clk_4m has Internal fmax of 81.97 MHz between source register fenpingqi:inst\|fenping5:b2v_inst4\|lpm_counter:s_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\] and destination register fenpingqi:inst\|fenping5:b2v_inst4\|cp9 (period= 12.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.300 ns + Longest register register " "Info: + Longest register to register delay is 9.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpingqi:inst\|fenping5:b2v_inst4\|lpm_counter:s_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\] 1 REG LC8_D36 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_D36; Fanout = 2; REG Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|lpm_counter:s_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { fenpingqi:inst|fenping5:b2v_inst4|lpm_counter:s_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.700 ns) 2.600 ns fenpingqi:inst\|fenping5:b2v_inst4\|i~214 2 COMB LC3_D35 1 " "Info: 2: + IC(0.900 ns) + CELL(1.700 ns) = 2.600 ns; Loc. = LC3_D35; Fanout = 1; COMB Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|i~214'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.600 ns" { fenpingqi:inst|fenping5:b2v_inst4|lpm_counter:s_rtl_9|alt_counter_f10ke:wysi_counter|q[15] fenpingqi:inst|fenping5:b2v_inst4|i~214 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 4.600 ns fenpingqi:inst\|fenping5:b2v_inst4\|i~218 3 COMB LC1_D35 18 " "Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 4.600 ns; Loc. = LC1_D35; Fanout = 18; COMB Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|i~218'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.000 ns" { fenpingqi:inst|fenping5:b2v_inst4|i~214 fenpingqi:inst|fenping5:b2v_inst4|i~218 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 6.300 ns fenpingqi:inst\|fenping5:b2v_inst4\|cp9~1 4 COMB LC2_D35 1 " "Info: 4: + IC(0.300 ns) + CELL(1.400 ns) = 6.300 ns; Loc. = LC2_D35; Fanout = 1; COMB Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|cp9~1'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "1.700 ns" { fenpingqi:inst|fenping5:b2v_inst4|i~218 fenpingqi:inst|fenping5:b2v_inst4|cp9~1 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.000 ns) 9.300 ns fenpingqi:inst\|fenping5:b2v_inst4\|cp9 5 REG LC2_A30 2 " "Info: 5: + IC(2.000 ns) + CELL(1.000 ns) = 9.300 ns; Loc. = LC2_A30; Fanout = 2; REG Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|cp9'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "3.000 ns" { fenpingqi:inst|fenping5:b2v_inst4|cp9~1 fenpingqi:inst|fenping5:b2v_inst4|cp9 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 62.37 % " "Info: Total cell delay = 5.800 ns ( 62.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns 37.63 % " "Info: Total interconnect delay = 3.500 ns ( 37.63 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "9.300 ns" { fenpingqi:inst|fenping5:b2v_inst4|lpm_counter:s_rtl_9|alt_counter_f10ke:wysi_counter|q[15] fenpingqi:inst|fenping5:b2v_inst4|i~214 fenpingqi:inst|fenping5:b2v_inst4|i~218 fenpingqi:inst|fenping5:b2v_inst4|cp9~1 fenpingqi:inst|fenping5:b2v_inst4|cp9 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.800 ns - Smallest " "Info: - Smallest clock skew is -1.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_4m destination 3.200 ns + Shortest register " "Info: + Shortest clock path from clock clk_4m to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk_4m 1 CLK Pin_55 145 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_55; Fanout = 145; CLK Node = 'clk_4m'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { clk_4m } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 120 -328 -160 136 "clk_4m" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns fenpingqi:inst\|fenping5:b2v_inst4\|cp8 2 REG LC8_A30 20 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC8_A30; Fanout = 20; REG Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|cp8'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "0.900 ns" { clk_4m fenpingqi:inst|fenping5:b2v_inst4|cp8 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 3.200 ns fenpingqi:inst\|fenping5:b2v_inst4\|cp9 3 REG LC2_A30 2 " "Info: 3: + IC(0.300 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC2_A30; Fanout = 2; REG Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|cp9'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "0.300 ns" { fenpingqi:inst|fenping5:b2v_inst4|cp8 fenpingqi:inst|fenping5:b2v_inst4|cp9 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 78.13 % " "Info: Total cell delay = 2.500 ns ( 78.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns 21.88 % " "Info: Total interconnect delay = 0.700 ns ( 21.88 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "3.200 ns" { clk_4m fenpingqi:inst|fenping5:b2v_inst4|cp8 fenpingqi:inst|fenping5:b2v_inst4|cp9 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_4m source 5.000 ns - Longest register " "Info: - Longest clock path from clock clk_4m to source register is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk_4m 1 CLK Pin_55 145 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_55; Fanout = 145; CLK Node = 'clk_4m'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { clk_4m } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 120 -328 -160 136 "clk_4m" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns fenpingqi:inst\|fenping5:b2v_inst4\|cp8 2 REG LC8_A30 20 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC8_A30; Fanout = 20; REG Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|cp8'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "0.900 ns" { clk_4m fenpingqi:inst|fenping5:b2v_inst4|cp8 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 5.000 ns fenpingqi:inst\|fenping5:b2v_inst4\|lpm_counter:s_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\] 3 REG LC8_D36 2 " "Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 5.000 ns; Loc. = LC8_D36; Fanout = 2; REG Node = 'fenpingqi:inst\|fenping5:b2v_inst4\|lpm_counter:s_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.100 ns" { fenpingqi:inst|fenping5:b2v_inst4|cp8 fenpingqi:inst|fenping5:b2v_inst4|lpm_counter:s_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 50.00 % " "Info: Total cell delay = 2.500 ns ( 50.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 50.00 % " "Info: Total interconnect delay = 2.500 ns ( 50.00 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "5.000 ns" { clk_4m fenpingqi:inst|fenping5:b2v_inst4|cp8 fenpingqi:inst|fenping5:b2v_inst4|lpm_counter:s_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } }  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "3.200 ns" { clk_4m fenpingqi:inst|fenping5:b2v_inst4|cp8 fenpingqi:inst|fenping5:b2v_inst4|cp9 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "5.000 ns" { clk_4m fenpingqi:inst|fenping5:b2v_inst4|cp8 fenpingqi:inst|fenping5:b2v_inst4|lpm_counter:s_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping5.vhd" 27 -1 0 } }  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "9.300 ns" { fenpingqi:inst|fenping5:b2v_inst4|lpm_counter:s_rtl_9|alt_counter_f10ke:wysi_counter|q[15] fenpingqi:inst|fenping5:b2v_inst4|i~214 fenpingqi:inst|fenping5:b2v_inst4|i~218 fenpingqi:inst|fenping5:b2v_inst4|cp9~1 fenpingqi:inst|fenping5:b2v_inst4|cp9 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "3.200 ns" { clk_4m fenpingqi:inst|fenping5:b2v_inst4|cp8 fenpingqi:inst|fenping5:b2v_inst4|cp9 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "5.000 ns" { clk_4m fenpingqi:inst|fenping5:b2v_inst4|cp8 fenpingqi:inst|fenping5:b2v_inst4|lpm_counter:s_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "WR " "Info: No valid register-to-register paths exist for clock WR" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ALE " "Info: No valid register-to-register paths exist for clock ALE" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "control:inst6\|data\[1\] P0\[1\] ALE 7.200 ns register " "Info: tsu for register control:inst6\|data\[1\] (data pin = P0\[1\], clock pin = ALE) is 7.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest pin register " "Info: + Longest pin to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns P0\[1\] 1 PIN Pin_39 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_39; Fanout = 1; PIN Node = 'P0\[1\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { P0[1] } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 24 -328 -160 40 "P0\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.800 ns) 9.000 ns control:inst6\|data\[1\] 2 REG LC2_B7 1 " "Info: 2: + IC(3.300 ns) + CELL(0.800 ns) = 9.000 ns; Loc. = LC2_B7; Fanout = 1; REG Node = 'control:inst6\|data\[1\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "4.100 ns" { P0[1] control:inst6|data[1] } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/control.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/control.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 63.33 % " "Info: Total cell delay = 5.700 ns ( 63.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns 36.67 % " "Info: Total interconnect delay = 3.300 ns ( 36.67 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "9.000 ns" { P0[1] control:inst6|data[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "D:/xiongxusheng/eda/boxingcunchu/control.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/control.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ALE destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock ALE to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ALE 1 CLK Pin_125 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 8; CLK Node = 'ALE'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { ALE } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 8 -328 -160 24 "ALE" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns control:inst6\|data\[1\] 2 REG LC2_B7 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_B7; Fanout = 1; REG Node = 'control:inst6\|data\[1\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "0.400 ns" { ALE control:inst6|data[1] } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/control.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/control.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.400 ns" { ALE control:inst6|data[1] } "NODE_NAME" } } }  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "9.000 ns" { P0[1] control:inst6|data[1] } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.400 ns" { ALE control:inst6|data[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_4m dataout\[2\] lpm_ram_dp0:inst3\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\] 19.200 ns memory " "Info: tco from clock clk_4m to destination pin dataout\[2\] through memory lpm_ram_dp0:inst3\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\] is 19.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_4m source 7.400 ns + Longest memory " "Info: + Longest clock path from clock clk_4m to source memory is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk_4m 1 CLK Pin_55 145 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_55; Fanout = 145; CLK Node = 'clk_4m'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { clk_4m } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 120 -328 -160 136 "clk_4m" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns fenpingqi:inst\|fenping3:b2v_inst2\|cp4 2 REG LC1_F5 20 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_F5; Fanout = 20; REG Node = 'fenpingqi:inst\|fenping3:b2v_inst2\|cp4'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "0.900 ns" { clk_4m fenpingqi:inst|fenping3:b2v_inst2|cp4 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/fenping3.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping3.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(0.500 ns) 5.800 ns fenpingqi:inst\|fenping3:b2v_inst2\|cp5 3 REG LC1_B18 121 " "Info: 3: + IC(2.400 ns) + CELL(0.500 ns) = 5.800 ns; Loc. = LC1_B18; Fanout = 121; REG Node = 'fenpingqi:inst\|fenping3:b2v_inst2\|cp5'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.900 ns" { fenpingqi:inst|fenping3:b2v_inst2|cp4 fenpingqi:inst|fenping3:b2v_inst2|cp5 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/fenping3.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/fenping3.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.000 ns) 7.400 ns lpm_ram_dp0:inst3\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\] 4 MEM EC1_B 1 " "Info: 4: + IC(1.600 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = EC1_B; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst3\|lpm_ram_dp:lpm_ram_dp_component\|altdpram:sram\|q\[2\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "1.600 ns" { fenpingqi:inst|fenping3:b2v_inst2|cp5 lpm_ram_dp0:inst3|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[2] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/altdpram.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/altdpram.tdf" 182 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 40.54 % " "Info: Total cell delay = 3.000 ns ( 40.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns 59.46 % " "Info: Total interconnect delay = 4.400 ns ( 59.46 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "7.400 ns" { clk_4m fenpingqi:inst|fenping3:b2v_inst2|cp4 fenpingqi:inst|fenping3:b2v_inst2|cp5 lpm_ram_dp0:inst3|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "c:/quartu