boxingcunchu.tan.qmsg

数字波形存储器VHDL源码

{ "Info" "ITDB_TH_RESULT" "control:inst6\|s\[1\] a\[1\] WR 0.300 ns register " "Info: th for register control:inst6\|s\[1\] (data pin = a\[1\], clock pin = WR) is 0.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR destination 2.400 ns + Longest register " "Info: + Longest clock path from clock WR to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns WR 1 CLK Pin_126 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_126; Fanout = 4; CLK Node = 'WR'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { WR } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { -8 -328 -160 8 "WR" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns control:inst6\|s\[1\] 2 REG LC4_A20 6 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_A20; Fanout = 6; REG Node = 'control:inst6\|s\[1\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "0.400 ns" { WR control:inst6|s[1] } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/control.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/control.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.400 ns" { WR control:inst6|s[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "D:/xiongxusheng/eda/boxingcunchu/control.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/control.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a\[1\] 1 PIN Pin_56 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_56; Fanout = 1; PIN Node = 'a\[1\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { a[1] } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { -24 -328 -160 -8 "a\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.800 ns) 3.400 ns control:inst6\|s\[1\] 2 REG LC4_A20 6 " "Info: 2: + IC(0.600 ns) + CELL(0.800 ns) = 3.400 ns; Loc. = LC4_A20; Fanout = 6; REG Node = 'control:inst6\|s\[1\]'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "1.400 ns" { a[1] control:inst6|s[1] } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/control.vhd" "" "" { Text "D:/xiongxusheng/eda/boxingcunchu/control.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 82.35 % " "Info: Total cell delay = 2.800 ns ( 82.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 17.65 % " "Info: Total interconnect delay = 0.600 ns ( 17.65 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "3.400 ns" { a[1] control:inst6|s[1] } "NODE_NAME" } } }  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.400 ns" { WR control:inst6|s[1] } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "3.400 ns" { a[1] control:inst6|s[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk_4m ad/cs xuanzhe:inst8\|clkout~reg0 10.000 ns register " "Info: Minimum tco from clock clk_4m to destination pin ad/cs through register xuanzhe:inst8\|clkout~reg0 is 10.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_4m source 2.400 ns + Shortest register " "Info: + Shortest clock path from clock clk_4m to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk_4m 1 CLK Pin_55 145 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_55; Fanout = 145; CLK Node = 'clk_4m'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { clk_4m } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 120 -328 -160 136 "clk_4m" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns xuanzhe:inst8\|clkout~reg0 2 REG LC1_C3 120 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_C3; Fanout = 120; REG Node = 'xuanzhe:inst8\|clkout~reg0'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "0.400 ns" { clk_4m xuanzhe:inst8|clkout~reg0 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/xuanzhe.vhd" "" "" { Text "D:/xiongxusheng/eda/xuanzhe.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.400 ns" { clk_4m xuanzhe:inst8|clkout~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "D:/xiongxusheng/eda/xuanzhe.vhd" "" "" { Text "D:/xiongxusheng/eda/xuanzhe.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.100 ns + Shortest register pin " "Info: + Shortest register to pin delay is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xuanzhe:inst8\|clkout~reg0 1 REG LC1_C3 120 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C3; Fanout = 120; REG Node = 'xuanzhe:inst8\|clkout~reg0'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "" { xuanzhe:inst8|clkout~reg0 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/xuanzhe.vhd" "" "" { Text "D:/xiongxusheng/eda/xuanzhe.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(6.300 ns) 7.100 ns ad/cs 2 PIN Pin_72 0 " "Info: 2: + IC(0.800 ns) + CELL(6.300 ns) = 7.100 ns; Loc. = Pin_72; Fanout = 0; PIN Node = 'ad/cs'" {  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "7.100 ns" { xuanzhe:inst8|clkout~reg0 ad/cs } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" "" "" { Schematic "D:/xiongxusheng/eda/boxingcunchu/boxingcunchu.bdf" { { 56 608 784 72 "ad/cs" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 88.73 % " "Info: Total cell delay = 6.300 ns ( 88.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 11.27 % " "Info: Total interconnect delay = 0.800 ns ( 11.27 % )" {  } {  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "7.100 ns" { xuanzhe:inst8|clkout~reg0 ad/cs } "NODE_NAME" } } }  } 0}  } { { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "2.400 ns" { clk_4m xuanzhe:inst8|clkout~reg0 } "NODE_NAME" } } } { "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" "" "" { Report "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu_cmp.qrpt" Compiler "boxingcunchu" "UNKNOWN" "V1" "D:/xiongxusheng/eda/boxingcunchu/db/boxingcunchu.quartus_db" { Floorplan "" "" "7.100 ns" { xuanzhe:inst8|clkout~reg0 ad/cs } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 04 09:41:26 2005 " "Info: Processing ended: Thu Aug 04 09:41:26 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}