fenping4.vhd

数字波形存储器VHDL源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenping4 is
   port(clk_4m:in std_logic;
         clk6,clk7:out std_logic);

end;
architecture art of  fenping4 is
signal  cp6 ,cp7 :std_logic;
signal count:std_logic_vector(15 downto 0);
signal s: std_logic_vector(15 downto 0);

      begin
 process(clk_4m) is
       begin
          if(clk_4m'event and clk_4m='1') then
                if count="0000000010000000" then
                  count<=(others=>'0');cp6<=not cp6;
                else count<=count+1;
          end if;
        end if;
        clk6<=cp6;
  end process;
process(cp6) is
        begin
        if(cp6'event and cp6='1') then
                if s="0000000000000010" then
                  s<=(others=>'0');cp7<=not cp7;
                else s<=s+1;
          end if;
        end if;
            clk7<=cp7;
        end process;
       
end;