boxingcunchu.map.rpt

数字波形存储器VHDL源码

+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 262   ;
; Number of registers using SLOAD      ; 0     ;
; Number of registers using ACLR       ; 0     ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 15    ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Aug 04 09:40:43 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off boxingcunchu -c boxingcunchu
Info: Found 2 design units and 1 entities in source file ../compare_4.vhd
    Info: Found design unit 1: compare_4-a
    Info: Found entity 1: compare_4
Info: Found 0 design units and 0 entities in source file ../fenping.vhd
Info: Found 0 design units and 0 entities in source file ../fd_dmc.vhd
Warning: Can't analyze file -- file D:/xiongxusheng/eda/boxingcunchu/fenping.vhd is missing
Info: Found 2 design units and 1 entities in source file fenping1.vhd
    Info: Found design unit 1: fenping1-art
    Info: Found entity 1: fenping1
Info: Found 2 design units and 1 entities in source file fenping2.vhd
    Info: Found design unit 1: fenping2-art
    Info: Found entity 1: fenping2
Info: Found 2 design units and 1 entities in source file fenping3.vhd
    Info: Found design unit 1: fenping3-art
    Info: Found entity 1: fenping3
Info: Found 2 design units and 1 entities in source file fenping4.vhd
    Info: Found design unit 1: fenping4-art
    Info: Found entity 1: fenping4
Info: Found 2 design units and 1 entities in source file fenping5.vhd
    Info: Found design unit 1: fenping5-art
    Info: Found entity 1: fenping5
Info: Found 2 design units and 1 entities in source file fenping6.vhd
    Info: Found design unit 1: fenping6-art
    Info: Found entity 1: fenping6
Info: Found 2 design units and 1 entities in source file fenping7.vhd
    Info: Found design unit 1: fenping7-art
    Info: Found entity 1: fenping7
Info: Found 2 design units and 1 entities in source file finping8.vhd
    Info: Found design unit 1: fenping8-art
    Info: Found entity 1: fenping8
Warning: Can't analyze file -- file D:/xiongxusheng/eda/boxingcunchu/fenping.bdf is missing
Info: Found 1 design units and 1 entities in source file boxingcunchu.bdf
    Info: Found entity 1: boxingcunchu
Info: Found 2 design units and 1 entities in source file ../sel_4.vhd
    Info: Found design unit 1: sel_4-a
    Info: Found entity 1: sel_4
Warning: Can't analyze file -- file D:/xiongxusheng/eda/boxingcunchu/compare_4.vhd is missing
Info: Found 2 design units and 1 entities in source file ../xuanzhe.vhd
    Info: Found design unit 1: xuanzhe-a
    Info: Found entity 1: xuanzhe
Info: Found 2 design units and 1 entities in source file fenpingqi.vhd
    Info: Found design unit 1: fenpingqi-bdf_type
    Info: Found entity 1: fenpingqi
Info: Found 2 design units and 1 entities in source file control.vhd
    Info: Found design unit 1: control-art
    Info: Found entity 1: control
Warning: VHDL Process Statement warning at fenping2.vhd(23): signal cp2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping2.vhd(33): signal cp3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping3.vhd(23): signal cp4 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping3.vhd(33): signal cp5 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping4.vhd(23): signal cp6 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping4.vhd(33): signal cp7 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping5.vhd(23): signal cp8 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping5.vhd(33): signal cp9 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping6.vhd(23): signal cp10 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping6.vhd(33): signal cp11 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping7.vhd(23): signal cp12 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping7.vhd(33): signal cp13 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at finping8.vhd(23): signal cp14 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at finping8.vhd(33): signal cp15 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping1.vhd(23): signal cp0 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at fenping1.vhd(33): signal cp1 is in statement, but is not in sensitivity list
Info: Using design file lpm_ram_dp0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_ram_dp0-SYN
    Info: Found entity 1: lpm_ram_dp0
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_ram_dp.tdf
    Info: Found entity 1: lpm_ram_dp
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altdpram.tdf
    Info: Found entity 1: altdpram
Info: Issued messaged during elaboration of megafunction lpm_ram_dp0:inst3|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram, which is child of megafunction lpm_ram_dp0:inst3|lpm_ram_dp:lpm_ram_dp_component
Info: Instantiated megafunction lpm_ram_dp0:inst3|lpm_ram_dp:lpm_ram_dp_component with the following parameter:
    Info: Parameter lpm_width = 8
    Info: Parameter lpm_widthad = 11
    Info: Parameter rden_used = FALSE
    Info: Parameter intended_device_family = ACEX1K
    Info: Parameter lpm_type = LPM_RAM_DP
    Info: Parameter lpm_indata = REGISTERED
    Info: Parameter lpm_wraddress_control = REGISTERED
    Info: Parameter lpm_rdaddress_control = REGISTERED
    Info: Parameter lpm_outdata = REGISTERED
    Info: Parameter use_eab = ON
Warning: Memory Initialization File or Hexadecimal (Intel-Format) File for RAM is not specified -- setting initial contents to 0
    Warning: RAM name is segment[0][7]
    Warning: RAM name is segment[0][6]
    Warning: RAM name is segment[0][5]
    Warning: RAM name is segment[0][4]
    Warning: RAM name is segment[0][3]
    Warning: RAM name is segment[0][2]
    Warning: RAM name is segment[0][1]
    Warning: RAM name is segment[0][0]
Info: Using design file latch_11.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: latch_11-SYN
    Info: Found entity 1: latch_11
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_latch.tdf
    Info: Found entity 1: lpm_latch
Info: Using design file counter_8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter_8-SYN
    Info: Found entity 1: counter_8
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Using design file counter_2048.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter_2048-SYN
    Info: Found entity 1: counter_2048
Info: Inferred 15 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping3:b2v_inst2|s[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping1:b2v_inst8|count[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping1:b2v_inst8|s[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping2:b2v_inst1|count[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping2:b2v_inst1|s[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping3:b2v_inst2|count[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping4:b2v_inst3|count[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping4:b2v_inst3|s[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping5:b2v_inst4|count[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping5:b2v_inst4|s[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping6:b2v_inst5|count[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping7:b2v_inst6|count[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping8:b2v_inst7|count[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping8:b2v_inst7|s[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: fenpingqi:inst|fenping7:b2v_inst6|s[0]~0
Info: Implemented 447 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 9 output pins
    Info: Implemented 415 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings
    Info: Processing ended: Thu Aug 04 09:40:54 2005
    Info: Elapsed time: 00:00:10