fenping1.vhd

数字波形存储器VHDL源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenping1 is
   port(clk_4m:in std_logic;
         clk0,clk1:out std_logic);

end;
architecture art of  fenping1 is
signal cp0,cp1 :std_logic;
signal count:std_logic_vector(15 downto 0);
signal s: std_logic_vector(15 downto 0);

      begin
 process(clk_4m) is
       begin
          if(clk_4m'event and clk_4m='1') then
                if count="0000000000000010" then
                  count<=(others=>'0');cp0<=not cp0;
                else count<=count+1;
          end if;
        end if;
        clk0<=cp0;
  end process;
process(cp0) is
        begin
        if(cp0'event and cp0='1') then
                if s="0000000000000010" then
                 s<=(others=>'0');cp1<=not cp1;
                else s<=s+1;
          end if;
        end if;
            clk1<=cp1;
        end process;
       
end;