fenpingqi.vhd

数字波形存储器VHDL源码

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY fenpingqi IS 
	port
	(
		clk_4m :  IN  STD_LOGIC;
		clk0 :  OUT  STD_LOGIC;
		clk1 :  OUT  STD_LOGIC;
		clk2 :  OUT  STD_LOGIC;
		clk3 :  OUT  STD_LOGIC;
		clk4 :  OUT  STD_LOGIC;
		clk5 :  OUT  STD_LOGIC;
		clk6 :  OUT  STD_LOGIC;
		clk7 :  OUT  STD_LOGIC;
		clk8 :  OUT  STD_LOGIC;
		clk9 :  OUT  STD_LOGIC;
		clk10 :  OUT  STD_LOGIC;
		clk11 :  OUT  STD_LOGIC;
		clk13 :  OUT  STD_LOGIC;
		clk14 :  OUT  STD_LOGIC;
		clk15 :  OUT  STD_LOGIC;
		clk12 :  OUT  STD_LOGIC
	);
END fenpingqi;

ARCHITECTURE bdf_type OF fenpingqi IS 



component fenping1
	PORT(clk_4m : IN STD_LOGIC;
		 clk0 : OUT STD_LOGIC;
		 clk1 : OUT STD_LOGIC
	);
end component;



component fenping2
	PORT(clk_4m : IN STD_LOGIC;
		 clk2 : OUT STD_LOGIC;
		 clk3 : OUT STD_LOGIC
	);
end component;

component fenping3
	PORT(clk_4m : IN STD_LOGIC;
		 clk4 : OUT STD_LOGIC;
		 clk5 : OUT STD_LOGIC
	);
end component;

component fenping4
	PORT(clk_4m : IN STD_LOGIC;
		 clk6 : OUT STD_LOGIC;
		 clk7 : OUT STD_LOGIC
	);
end component;

component fenping5
	PORT(clk_4m : IN STD_LOGIC;
		 clk8 : OUT STD_LOGIC;
		 clk9 : OUT STD_LOGIC
	);
end component;

component fenping6
	PORT(clk_4m : IN STD_LOGIC;
		 clk10 : OUT STD_LOGIC;
		 clk11 : OUT STD_LOGIC
	);
end component;

component fenping7
	PORT(clk_4m : IN STD_LOGIC;
		 clk12 : OUT STD_LOGIC;
		 clk13 : OUT STD_LOGIC
	);
end component;

component fenping8
	PORT(clk_4m : IN STD_LOGIC;
		 clk14 : OUT STD_LOGIC;
		 clk15 : OUT STD_LOGIC
	);
end component;

signal	s0 :  STD_LOGIC;
signal	s1 :  STD_LOGIC;
signal	s10 :  STD_LOGIC;
signal	s11 :  STD_LOGIC;
signal	s12 :  STD_LOGIC;
signal	s13 :  STD_LOGIC;
signal	s14 :  STD_LOGIC;
signal	s15 :  STD_LOGIC;
signal	s2 :  STD_LOGIC;
signal	s3 :  STD_LOGIC;
signal	s4 :  STD_LOGIC;
signal	s5 :  STD_LOGIC;
signal	s6 :  STD_LOGIC;
signal	s7 :  STD_LOGIC;
signal	s8 :  STD_LOGIC;
signal	s9 :  STD_LOGIC;


BEGIN 



b2v_inst1 : fenping2
PORT MAP(clk_4m => clk_4m,
		 clk2 => s2,
		 clk3 => s3);

b2v_inst2 : fenping3
PORT MAP(clk_4m => clk_4m,
		 clk4 => s4,
		 clk5 => s5);

b2v_inst3 : fenping4
PORT MAP(clk_4m => clk_4m,
		 clk6 => s6,
		 clk7 => s7);

b2v_inst4 : fenping5
PORT MAP(clk_4m => clk_4m,
		 clk8 => s8,
		 clk9 => s9);

b2v_inst5 : fenping6
PORT MAP(clk_4m => clk_4m,
		 clk10 => s10,
		 clk11 => s11);

b2v_inst6 : fenping7
PORT MAP(clk_4m => clk_4m,
		 clk12 => s12,
		 clk13 => s13);

b2v_inst7 : fenping8
PORT MAP(clk_4m => clk_4m,
		 clk14 => s14,
		 clk15 => s15);

b2v_inst8 : fenping1
PORT MAP(clk_4m => clk_4m,
		 clk0 => s0,
		 clk1 => s1);
clk0 <= s0;
clk1 <= s1;
clk2 <= s2;
clk3 <= s3;
clk4 <= s4;
clk5 <= s5;
clk6 <= s6;
clk7 <= s7;
clk8 <= s8;
clk9 <= s9;
clk10 <= s10;
clk11 <= s11;
clk13 <= s13;
clk14 <= s14;
clk15 <= s15;
clk12 <= s12;

END;