fenping7.vhd

数字波形存储器VHDL源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenping7 is
   port(clk_4m:in std_logic;
         clk12,clk13:out std_logic);

end;
architecture art of  fenping7 is
signal  cp12 ,cp13 :std_logic;
signal count:std_logic_vector(15 downto 0);
signal s: std_logic_vector(15 downto 0);

      begin
 process(clk_4m) is
       begin
          if(clk_4m'event and clk_4m='1') then
                if s="0010000000000000" then
                 s<=(others=>'0');cp12<=not cp12;
                else s<=s+1;
          end if;
        end if;
        clk12<=cp12;
  end process;
process(cp12) is
        begin
        if(cp12'event and cp12='1') then
                if count="0000000000000010" then
                  count<=(others=>'0');cp13<=not cp13;
                else count<=count+1;
          end if;
        end if;
            clk13<=cp13;
        end process;
       
end;