csc_top.par

现色彩空间转换R’G’B’ to Y’CbCr的VHDL源代码。

Release 4.2.03i - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Fri Aug 02 15:18:11 2002

par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcf


Constraints file: csc_top.pcf

Loading design for application par from file csc_top_map.ncd.
   "csc_top" is an NCD, version 2.37, device xc2s30, package tq144, speed -5
Loading device for application par from file '2s30.nph' in environment C:/ISE42.
Device speed data version:  PRELIMINARY 1.23 2001-12-19.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            62 out of 92     67%
      Number of LOCed External IOBs    0 out of 62      0%

   Number of SLICEs                  283 out of 432    65%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   5 (set by user)
Placer effort level (-pl):    5 (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    5 (default)
Extra effort level (-xe):     1 (default)

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 

Starting initial Placement phase. REAL time: 3 secs 
Finished initial Placement phase. REAL time: 3 secs 
Starting the placer. REAL time: 3 secs 
Placement pass 1 .....
Placer score = 49265
Placement pass 2 ...........
Placer score = 53706
Placement pass 3 ...............
Placer score = 52728
Placement pass 4 .........
Placer score = 50553
Placement pass 5 ......................
Placer score = 55087
Placement pass 6 ...........................
Placer score = 55301
Optimizing ... 
Placer score = 51678
Placer score = 51471
Placer score = 51529
Placer score = 51237
Placer score = 51280
Placer score = 51475
Placer score = 51310
Placer score = 51340
Placer score = 51277
Placer score = 51265
Placer stage completed in real time: 7 secs 

Optimizing ... 
Placer score = 45593
Placer completed in real time: 8 secs 

Dumping design to file csc_top.ncd.

Total REAL time to Placer completion: 8 secs 
Total CPU time to Placer completion: 5 secs 

0 connection(s) routed; 1783 unrouted active, 37 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 8 secs 
Starting iterative routing. 
Routing active signals.
.............
Optimizing (1526).
.................................................................................................................
End of iteration 1 
1820 successful; 0 unrouted; (3491) REAL time: 29 secs 
..End of iteration 2 
1820 successful; 0 unrouted; (1934) REAL time: 57 secs 
WARNING:Route:260 - Routing for this placement is not expected to meet the
   current timing constraints.  Change the placement, modify the timing
   constraints or reduce the number of logic levels in the paths that are not
   meeting timing.
Total REAL time: 57 secs 
Total CPU  time: 33 secs 
End of route.  1820 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

The design submitted for place and route did not meet the specified timing
requirements.  Please use the static timing analysis tools (TRCE or Timing
Analyzer) to report which constraints were not met.  To obtain a better result,
you may try the following:
  * Use the Re-entrant routing feature to run more router iterations on the
design.
  * Check the timing constraints to make sure the design is not
over-constrained.
  * Specify a higher placer effort level, if possible.
  * Use the Multi-Pass PAR (MPPR) feature.  This generates multiple placement
trials from which the best (i.e., lowest design score) placement can be used
with re-entrant routing to obtain a better result.

Please consult the Development System Reference Guide for more detailed
information about the usage options pertaining to these features.

Total REAL time to Router completion: 57 secs 
Total CPU time to Router completion: 33 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 1339


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        2.044 ns
   The Maximum Pin Delay is:                               8.168 ns
   The Average Connection Delay on the 10 Worst Nets is:   4.818 ns

   Listing Pin Delays by value: (ns)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 9.00  d >= 9.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1126         435         170          86           3           0

Timing Score: 1934

WARNING:Par:62 - Timing constraints have not been met.

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
* NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 14.434ns   | 14   
  S   HIGH 50.000000 %                      |            |            |      
--------------------------------------------------------------------------------
  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 8.414ns    | 3    
--------------------------------------------------------------------------------
  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 7.620ns    | 1    
--------------------------------------------------------------------------------


1 constraint not met.
Dumping design to file csc_top.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 1 mins 
Total CPU time to PAR completion: 34 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - 1 errors found.

PAR done.