csc_top.par

现色彩空间转换R’G’B’ to Y’CbCr的VHDL源代码。

Release 4.2.03i - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Fri Aug 02 15:19:47 2002

par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcf


Constraints file: csc_top.pcf

Loading design for application par from file csc_top_map.ncd.
   "csc_top" is an NCD, version 2.37, device xc2v80, package cs144, speed -4
Loading device for application par from file '2v80.nph' in environment C:/ISE42.
The STEPPING level for this design is 1.
Device speed data version:  PRODUCTION 1.105 2002-05-09.


Device utilization summary:

   Number of External IOBs            63 out of 92     68%
      Number of LOCed External IOBs    0 out of 63      0%

   Number of SLICEs                  287 out of 512    56%

   Number of BUFGMUXs                  1 out of 16      6%



Overall effort level (-ol):   5 (set by user)
Placer effort level (-pl):    5 (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    5 (default)
Extra effort level (-xe):     1 (default)

Starting initial Timing Analysis.  REAL time: 9 secs 
Finished initial Timing Analysis.  REAL time: 12 secs 

Starting Clock Logic Placement.  REAL time: 14 secs 

Finished Clock Logic Placement.  REAL time: 15 secs 

Automatic resolution of clock placement was successful.
It was not necessary to constrain the placement of any of the logic driven by
the global clocks with the current clock placement.

######################################################
## Automatic clock placement completed.
######################################################

Starting clustering phase.  REAL time: 31 secs 
Finished clustering phase.  REAL time: 35 secs 

Starting Mincut Placer.  REAL time: 35 secs 
Finished Mincut Placer.  REAL time: 35 secs 

Dumping design to file csc_top.ncd.

Starting Directed Placer.  REAL time: 37 secs 
Placement pass 1 .........

Placer score = 147265
Placement pass 2 .........

Placer score = 119064
Placement pass 3 ........

Placer score = 186914
Placer score = 119064
Finished Directed Placer.  REAL time: 43 secs 

Starting Constructive Placer.  REAL time: 44 secs 
Placer score = 80442
Placer score = 74270
Placer score = 71118
Placer score = 68168
Placer score = 62926
Placer score = 59749
Placer score = 58473
Placer score = 54590
Placer score = 54384
Placer score = 54290
Placer score = 52395
Placer score = 51300
Placer score = 51190
Placer score = 50660
Placer score = 50325
Placer score = 50190
Finished Constructive Placer.  REAL time: 56 secs 

Dumping design to file csc_top.ncd.

Starting Optimizing Placer.  REAL time: 57 secs 
Optimizing  
Swapped 92 comps.
Xilinx Placer [1]   48160   REAL time: 57 secs 
Optimizing  
Swapped 18 comps.
Xilinx Placer [2]   47850   REAL time: 58 secs 
Optimizing  
Swapped 3 comps.
Xilinx Placer [3]   47835   REAL time: 58 secs 
Finished Optimizing Placer.  REAL time: 58 secs 

Dumping design to file csc_top.ncd.

Total REAL time to Placer completion: 59 secs 
Total CPU time to Placer completion: 13 secs 

0 connection(s) routed; 2058 unrouted active, 33 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 1 mins 2 secs 
Starting iterative routing. 
Routing active signals.
..........
End of iteration 1 
2091 successful; 0 unrouted; (0) REAL time: 1 mins 16 secs 
Constraints are met. 
Total REAL time: 1 mins 17 secs 
Total CPU  time: 17 secs 
End of route.  2091 routed (100.00%); 0 unrouted.
No errors found. 
WARNING:Route:49 - The signal "GLOBAL_LOGIC0" has no loads so was not routed. 

Total REAL time to Router completion: 1 mins 18 secs 
Total CPU time to Router completion: 17 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 5189


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.184 ns
   The Maximum Pin Delay is:                               4.114 ns
   The Average Connection Delay on the 10 Worst Nets is:   3.552 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1093         525         340         128           5           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 11.986ns   | 14   
  S   HIGH 50.000000 %                      |            |            |      
--------------------------------------------------------------------------------
  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 4.143ns    | 3    
--------------------------------------------------------------------------------
  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 8.705ns    | 1    
--------------------------------------------------------------------------------


All constraints were met.
Dumping design to file csc_top.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 1 mins 23 secs 
Total CPU time to PAR completion: 18 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

PAR done.