reserv.map.eqn

采用高速AD的存储示波器设计

NB1_q_b[4]_PORT_B_data_in_reg = DFFE(NB1_q_b[4]_PORT_B_data_in, NB1_q_b[4]_clock_1, , , );
NB1_q_b[4]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[4]_PORT_A_address_reg = DFFE(NB1_q_b[4]_PORT_A_address, NB1_q_b[4]_clock_0, , , );
NB1_q_b[4]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[4]_PORT_B_address_reg = DFFE(NB1_q_b[4]_PORT_B_address, NB1_q_b[4]_clock_1, , , );
NB1_q_b[4]_PORT_A_write_enable = KEY1;
NB1_q_b[4]_PORT_A_write_enable_reg = DFFE(NB1_q_b[4]_PORT_A_write_enable, NB1_q_b[4]_clock_0, , , );
NB1_q_b[4]_PORT_B_write_enable = PB1L33;
NB1_q_b[4]_PORT_B_write_enable_reg = DFFE(NB1_q_b[4]_PORT_B_write_enable, NB1_q_b[4]_clock_1, , , );
NB1_q_b[4]_clock_0 = CLK;
NB1_q_b[4]_clock_1 = A1L51;
NB1_q_b[4]_PORT_B_data_out = MEMORY(NB1_q_b[4]_PORT_A_data_in_reg, NB1_q_b[4]_PORT_B_data_in_reg, NB1_q_b[4]_PORT_A_address_reg, NB1_q_b[4]_PORT_B_address_reg, NB1_q_b[4]_PORT_A_write_enable_reg, NB1_q_b[4]_PORT_B_write_enable_reg, , , NB1_q_b[4]_clock_0, NB1_q_b[4]_clock_1, , , , );
NB1_q_b[4] = NB1_q_b[4]_PORT_B_data_out[0];


--NB1_q_a[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[3]_PORT_A_data_in = DIN[3];
NB1_q_a[3]_PORT_A_data_in_reg = DFFE(NB1_q_a[3]_PORT_A_data_in, NB1_q_a[3]_clock_0, , , );
NB1_q_a[3]_PORT_B_data_in = PB1_ram_rom_data_reg[3];
NB1_q_a[3]_PORT_B_data_in_reg = DFFE(NB1_q_a[3]_PORT_B_data_in, NB1_q_a[3]_clock_1, , , );
NB1_q_a[3]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[3]_PORT_A_address_reg = DFFE(NB1_q_a[3]_PORT_A_address, NB1_q_a[3]_clock_0, , , );
NB1_q_a[3]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[3]_PORT_B_address_reg = DFFE(NB1_q_a[3]_PORT_B_address, NB1_q_a[3]_clock_1, , , );
NB1_q_a[3]_PORT_A_write_enable = KEY1;
NB1_q_a[3]_PORT_A_write_enable_reg = DFFE(NB1_q_a[3]_PORT_A_write_enable, NB1_q_a[3]_clock_0, , , );
NB1_q_a[3]_PORT_B_write_enable = PB1L33;
NB1_q_a[3]_PORT_B_write_enable_reg = DFFE(NB1_q_a[3]_PORT_B_write_enable, NB1_q_a[3]_clock_1, , , );
NB1_q_a[3]_clock_0 = CLK;
NB1_q_a[3]_clock_1 = A1L51;
NB1_q_a[3]_PORT_A_data_out = MEMORY(NB1_q_a[3]_PORT_A_data_in_reg, NB1_q_a[3]_PORT_B_data_in_reg, NB1_q_a[3]_PORT_A_address_reg, NB1_q_a[3]_PORT_B_address_reg, NB1_q_a[3]_PORT_A_write_enable_reg, NB1_q_a[3]_PORT_B_write_enable_reg, , , NB1_q_a[3]_clock_0, NB1_q_a[3]_clock_1, , , , );
NB1_q_a[3] = NB1_q_a[3]_PORT_A_data_out[0];

--NB1_q_b[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[3]
NB1_q_b[3]_PORT_A_data_in = DIN[3];
NB1_q_b[3]_PORT_A_data_in_reg = DFFE(NB1_q_b[3]_PORT_A_data_in, NB1_q_b[3]_clock_0, , , );
NB1_q_b[3]_PORT_B_data_in = PB1_ram_rom_data_reg[3];
NB1_q_b[3]_PORT_B_data_in_reg = DFFE(NB1_q_b[3]_PORT_B_data_in, NB1_q_b[3]_clock_1, , , );
NB1_q_b[3]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[3]_PORT_A_address_reg = DFFE(NB1_q_b[3]_PORT_A_address, NB1_q_b[3]_clock_0, , , );
NB1_q_b[3]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[3]_PORT_B_address_reg = DFFE(NB1_q_b[3]_PORT_B_address, NB1_q_b[3]_clock_1, , , );
NB1_q_b[3]_PORT_A_write_enable = KEY1;
NB1_q_b[3]_PORT_A_write_enable_reg = DFFE(NB1_q_b[3]_PORT_A_write_enable, NB1_q_b[3]_clock_0, , , );
NB1_q_b[3]_PORT_B_write_enable = PB1L33;
NB1_q_b[3]_PORT_B_write_enable_reg = DFFE(NB1_q_b[3]_PORT_B_write_enable, NB1_q_b[3]_clock_1, , , );
NB1_q_b[3]_clock_0 = CLK;
NB1_q_b[3]_clock_1 = A1L51;
NB1_q_b[3]_PORT_B_data_out = MEMORY(NB1_q_b[3]_PORT_A_data_in_reg, NB1_q_b[3]_PORT_B_data_in_reg, NB1_q_b[3]_PORT_A_address_reg, NB1_q_b[3]_PORT_B_address_reg, NB1_q_b[3]_PORT_A_write_enable_reg, NB1_q_b[3]_PORT_B_write_enable_reg, , , NB1_q_b[3]_clock_0, NB1_q_b[3]_clock_1, , , , );
NB1_q_b[3] = NB1_q_b[3]_PORT_B_data_out[0];


--NB1_q_a[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[2]_PORT_A_data_in = DIN[2];
NB1_q_a[2]_PORT_A_data_in_reg = DFFE(NB1_q_a[2]_PORT_A_data_in, NB1_q_a[2]_clock_0, , , );
NB1_q_a[2]_PORT_B_data_in = PB1_ram_rom_data_reg[2];
NB1_q_a[2]_PORT_B_data_in_reg = DFFE(NB1_q_a[2]_PORT_B_data_in, NB1_q_a[2]_clock_1, , , );
NB1_q_a[2]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[2]_PORT_A_address_reg = DFFE(NB1_q_a[2]_PORT_A_address, NB1_q_a[2]_clock_0, , , );
NB1_q_a[2]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[2]_PORT_B_address_reg = DFFE(NB1_q_a[2]_PORT_B_address, NB1_q_a[2]_clock_1, , , );
NB1_q_a[2]_PORT_A_write_enable = KEY1;
NB1_q_a[2]_PORT_A_write_enable_reg = DFFE(NB1_q_a[2]_PORT_A_write_enable, NB1_q_a[2]_clock_0, , , );
NB1_q_a[2]_PORT_B_write_enable = PB1L33;
NB1_q_a[2]_PORT_B_write_enable_reg = DFFE(NB1_q_a[2]_PORT_B_write_enable, NB1_q_a[2]_clock_1, , , );
NB1_q_a[2]_clock_0 = CLK;
NB1_q_a[2]_clock_1 = A1L51;
NB1_q_a[2]_PORT_A_data_out = MEMORY(NB1_q_a[2]_PORT_A_data_in_reg, NB1_q_a[2]_PORT_B_data_in_reg, NB1_q_a[2]_PORT_A_address_reg, NB1_q_a[2]_PORT_B_address_reg, NB1_q_a[2]_PORT_A_write_enable_reg, NB1_q_a[2]_PORT_B_write_enable_reg, , , NB1_q_a[2]_clock_0, NB1_q_a[2]_clock_1, , , , );
NB1_q_a[2] = NB1_q_a[2]_PORT_A_data_out[0];

--NB1_q_b[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[2]
NB1_q_b[2]_PORT_A_data_in = DIN[2];
NB1_q_b[2]_PORT_A_data_in_reg = DFFE(NB1_q_b[2]_PORT_A_data_in, NB1_q_b[2]_clock_0, , , );
NB1_q_b[2]_PORT_B_data_in = PB1_ram_rom_data_reg[2];
NB1_q_b[2]_PORT_B_data_in_reg = DFFE(NB1_q_b[2]_PORT_B_data_in, NB1_q_b[2]_clock_1, , , );
NB1_q_b[2]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[2]_PORT_A_address_reg = DFFE(NB1_q_b[2]_PORT_A_address, NB1_q_b[2]_clock_0, , , );
NB1_q_b[2]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[2]_PORT_B_address_reg = DFFE(NB1_q_b[2]_PORT_B_address, NB1_q_b[2]_clock_1, , , );
NB1_q_b[2]_PORT_A_write_enable = KEY1;
NB1_q_b[2]_PORT_A_write_enable_reg = DFFE(NB1_q_b[2]_PORT_A_write_enable, NB1_q_b[2]_clock_0, , , );
NB1_q_b[2]_PORT_B_write_enable = PB1L33;
NB1_q_b[2]_PORT_B_write_enable_reg = DFFE(NB1_q_b[2]_PORT_B_write_enable, NB1_q_b[2]_clock_1, , , );
NB1_q_b[2]_clock_0 = CLK;
NB1_q_b[2]_clock_1 = A1L51;
NB1_q_b[2]_PORT_B_data_out = MEMORY(NB1_q_b[2]_PORT_A_data_in_reg, NB1_q_b[2]_PORT_B_data_in_reg, NB1_q_b[2]_PORT_A_address_reg, NB1_q_b[2]_PORT_B_address_reg, NB1_q_b[2]_PORT_A_write_enable_reg, NB1_q_b[2]_PORT_B_write_enable_reg, , , NB1_q_b[2]_clock_0, NB1_q_b[2]_clock_1, , , , );
NB1_q_b[2] = NB1_q_b[2]_PORT_B_data_out[0];


--NB1_q_a[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[1]_PORT_A_data_in = DIN[1];
NB1_q_a[1]_PORT_A_data_in_reg = DFFE(NB1_q_a[1]_PORT_A_data_in, NB1_q_a[1]_clock_0, , , );
NB1_q_a[1]_PORT_B_data_in = PB1_ram_rom_data_reg[1];
NB1_q_a[1]_PORT_B_data_in_reg = DFFE(NB1_q_a[1]_PORT_B_data_in, NB1_q_a[1]_clock_1, , , );
NB1_q_a[1]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[1]_PORT_A_address_reg = DFFE(NB1_q_a[1]_PORT_A_address, NB1_q_a[1]_clock_0, , , );
NB1_q_a[1]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[1]_PORT_B_address_reg = DFFE(NB1_q_a[1]_PORT_B_address, NB1_q_a[1]_clock_1, , , );
NB1_q_a[1]_PORT_A_write_enable = KEY1;
NB1_q_a[1]_PORT_A_write_enable_reg = DFFE(NB1_q_a[1]_PORT_A_write_enable, NB1_q_a[1]_clock_0, , , );
NB1_q_a[1]_PORT_B_write_enable = PB1L33;
NB1_q_a[1]_PORT_B_write_enable_reg = DFFE(NB1_q_a[1]_PORT_B_write_enable, NB1_q_a[1]_clock_1, , , );
NB1_q_a[1]_clock_0 = CLK;
NB1_q_a[1]_clock_1 = A1L51;
NB1_q_a[1]_PORT_A_data_out = MEMORY(NB1_q_a[1]_PORT_A_data_in_reg, NB1_q_a[1]_PORT_B_data_in_reg, NB1_q_a[1]_PORT_A_address_reg, NB1_q_a[1]_PORT_B_address_reg, NB1_q_a[1]_PORT_A_write_enable_reg, NB1_q_a[1]_PORT_B_write_enable_reg, , , NB1_q_a[1]_clock_0, NB1_q_a[1]_clock_1, , , , );
NB1_q_a[1] = NB1_q_a[1]_PORT_A_data_out[0];

--NB1_q_b[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[1]
NB1_q_b[1]_PORT_A_data_in = DIN[1];
NB1_q_b[1]_PORT_A_data_in_reg = DFFE(NB1_q_b[1]_PORT_A_data_in, NB1_q_b[1]_clock_0, , , );
NB1_q_b[1]_PORT_B_data_in = PB1_ram_rom_data_reg[1];
NB1_q_b[1]_PORT_B_data_in_reg = DFFE(NB1_q_b[1]_PORT_B_data_in, NB1_q_b[1]_clock_1, , , );
NB1_q_b[1]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[1]_PORT_A_address_reg = DFFE(NB1_q_b[1]_PORT_A_address, NB1_q_b[1]_clock_0, , , );
NB1_q_b[1]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[1]_PORT_B_address_reg = DFFE(NB1_q_b[1]_PORT_B_address, NB1_q_b[1]_clock_1, , , );
NB1_q_b[1]_PORT_A_write_enable = KEY1;
NB1_q_b[1]_PORT_A_write_enable_reg = DFFE(NB1_q_b[1]_PORT_A_write_enable, NB1_q_b[1]_clock_0, , , );
NB1_q_b[1]_PORT_B_write_enable = PB1L33;
NB1_q_b[1]_PORT_B_write_enable_reg = DFFE(NB1_q_b[1]_PORT_B_write_enable, NB1_q_b[1]_clock_1, , , );
NB1_q_b[1]_clock_0 = CLK;
NB1_q_b[1]_clock_1 = A1L51;
NB1_q_b[1]_PORT_B_data_out = MEMORY(NB1_q_b[1]_PORT_A_data_in_reg, NB1_q_b[1]_PORT_B_data_in_reg, NB1_q_b[1]_PORT_A_address_reg, NB1_q_b[1]_PORT_B_address_reg, NB1_q_b[1]_PORT_A_write_enable_reg, NB1_q_b[1]_PORT_B_write_enable_reg, , , NB1_q_b[1]_clock_0, NB1_q_b[1]_clock_1, , , , );
NB1_q_b[1] = NB1_q_b[1]_PORT_B_data_out[0];


--NB1_q_a[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[0]_PORT_A_data_in = DIN[0];
NB1_q_a[0]_PORT_A_data_in_reg = DFFE(NB1_q_a[0]_PORT_A_data_in, NB1_q_a[0]_clock_0, , , );
NB1_q_a[0]_PORT_B_data_in = PB1_ram_rom_data_reg[0];
NB1_q_a[0]_PORT_B_data_in_reg = DFFE(NB1_q_a[0]_PORT_B_data_in, NB1_q_a[0]_clock_1, , , );
NB1_q_a[0]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[0]_PORT_A_address_reg = DFFE(NB1_q_a[0]_PORT_A_address, NB1_q_a[0]_clock_0, , , );
NB1_q_a[0]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[0]_PORT_B_address_reg = DFFE(NB1_q_a[0]_PORT_B_address, NB1_q_a[0]_clock_1, , , );
NB1_q_a[0]_PORT_A_write_enable = KEY1;
NB1_q_a[0]_PORT_A_write_enable_reg = DFFE(NB1_q_a[0]_PORT_A_write_enable, NB1_q_a[0]_clock_0, , , );
NB1_q_a[0]_PORT_B_write_enable = PB1L33;
NB1_q_a[0]_PORT_B_write_enable_reg = DFFE(NB1_q_a[0]_PORT_B_write_enable, NB1_q_a[0]_clock_1, , , );
NB1_q_a[0]_clock_0 = CLK;
NB1_q_a[0]_clock_1 = A1L51;
NB1_q_a[0]_PORT_A_data_out = MEMORY(NB1_q_a[0]_PORT_A_data_in_reg, NB1_q_a[0]_PORT_B_data_in_reg, NB1_q_a[0]_PORT_A_address_reg, NB1_q_a[0]_PORT_B_address_reg, NB1_q_a[0]_PORT_A_write_enable_reg, NB1_q_a[0]_PORT_B_write_enable_reg, , , NB1_q_a[0]_clock_0, NB1_q_a[0]_clock_1, , , , );
NB1_q_a[0] = NB1_q_a[0]_PORT_A_data_out[0];

--NB1_q_b[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[0]
NB1_q_b[0]_PORT_A_data_in = DIN[0];
NB1_q_b[0]_PORT_A_data_in_reg = DFFE(NB1_q_b[0]_PORT_A_data_in, NB1_q_b[0]_clock_0, , , );
NB1_q_b[0]_PORT_B_data_in = PB1_ram_rom_data_reg[0];
NB1_q_b[0]_PORT_B_data_in_reg = DFFE(NB1_q_b[0]_PORT_B_data_in, NB1_q_b[0]_clock_1, , , );
NB1_q_b[0]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[0]_PORT_A_address_reg = DFFE(NB1_q_b[0]_PORT_A_address, NB1_q_b[0]_clock_0, , , );
NB1_q_b[0]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[0]_PORT_B_address_reg = DFFE(NB1_q_b[0]_PORT_B_address, NB1_q_b[0]_clock_1, , , );
NB1_q_b[0]_PORT_A_write_enable = KEY1;
NB1_q_b[0]_PORT_A_write_enable_reg = DFFE(NB1_q_b[0]_PORT_A_write_enable, NB1_q_b[0]_clock_0, , , );
NB1_q_b[0]_PORT_B_write_enable = PB1L33;
NB1_q_b[0]_PORT_B_write_enable_reg = DFFE(NB1_q_b[0]_PORT_B_write_enable, NB1_q_b[0]_clock_1, , , );
NB1_q_b[0]_clock_0 = CLK;
NB1_q_b[0]_clock_1 = A1L51;
NB1_q_b[0]_PORT_B_data_out = MEMORY(NB1_q_b[0]_PORT_A_data_in_reg, NB1_q_b[0]_PORT_B_data_in_reg, NB1_q_b[0]_PORT_A_address_reg, NB1_q_b[0]_PORT_B_address_reg, NB1_q_b[0]_PORT_A_write_enable_reg, NB1_q_b[0]_PORT_B_write_enable_reg, , , NB1_q_b[0]_clock_0, NB1_q_b[0]_clock_1, , , , );
NB1_q_b[0] = NB1_q_b[0]_PORT_B_data_out[0];


--A1L61 is altera_internal_jtag~TDO
A1L61 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L52Q);

--A1L71 is altera_internal_jtag~TMSUTAP
A1L71 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L52Q);

--A1L51 is altera_internal_jtag~TCKUTAP
A1L51 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L52Q);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L52Q);


--PB1_ram_rom_incr_write_addr_reg is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg
--operation mode is normal

PB1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L51, PB1_ram_rom_load_read_data, VCC);


--HB1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

HB1_Q[2] = AMPP_FUNCTION(A1L51, HB3_Q[2], HB8_Q[2], HB5_Q[0], !D1L2, D1L83);


--PB1L33 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1
--operation mode is normal

PB1L33 = AMPP_FUNCTION(PB1_ram_rom_incr_write_addr_reg, HB1_Q[2]);


--DIN[7] is DIN[7]
--operation mode is normal

DIN[7]_lut_out = ADIN[7];
DIN[7] = DFFEA(DIN[7]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[7] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
--operation mode is normal

PB1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[7], altera_internal_jtag, NB1_q_b[7], PB1L01, VCC, PB1L9);


--QB1_safe_q[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[0]
--operation mode is arithmetic

QB1_safe_q[0] = AMPP_FUNCTION(A1L51, QB1_safe_q[0], PB1L31, !HB1_Q[0], PB1_ram_rom_incr_addr);

--QB1L2 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

QB1L2 = AMPP_FUNCTION(QB1_safe_q[0]);


--QB1_safe_q[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[1]
--operation mode is arithmetic

QB1_safe_q[1] = AMPP_FUNCTION(A1L51, QB1_safe_q[1], PB1L41, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L2);

--QB1L4 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

QB1L4 = AMPP_FUNCTION(QB1_safe_q[1], QB1L2);


--QB1_safe_q[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[2]
--operation mode is arithmetic

QB1_safe_q[2] = AMPP_FUNCTION(A1L51, QB1_safe_q[2], PB1L51, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L4);

--QB1L6 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

QB1L6 = AMPP_FUNCTION(QB1_safe_q[2], QB1L4);


--QB1_safe_q[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[3]
--operation mode is arithmetic

QB1_safe_q[3] = AMPP_FUNCTION(A1L51, QB1_safe_q[3], PB1L61, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L6);

--QB1L8 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

QB1L8 = AMPP_FUNCTION(QB1_safe_q[3], QB1L6);


--QB1_safe_q[4] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[4]
--operation mode is arithmetic

QB1_safe_q[4] = AMPP_FUNCTION(A1L51, QB1_safe_q[4], PB1L71, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L8);

--QB1L01 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella4~COUT