reserv.map.eqn

采用高速AD的存储示波器设计

--F1_safe_q[9] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[9]
--operation mode is normal

F1_safe_q[9]_carry_eqn = F1L81;
F1_safe_q[9]_lut_out = F1_safe_q[9] $ F1_safe_q[9]_carry_eqn;
F1_safe_q[9] = DFFEA(F1_safe_q[9]_lut_out, CLK, VCC, , , , );


--F1_safe_q[8] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[8]
--operation mode is arithmetic

F1_safe_q[8]_carry_eqn = F1L61;
F1_safe_q[8]_lut_out = F1_safe_q[8] $ !F1_safe_q[8]_carry_eqn;
F1_safe_q[8] = DFFEA(F1_safe_q[8]_lut_out, CLK, VCC, , , , );

--F1L81 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella8~COUT
--operation mode is arithmetic

F1L81 = CARRY(F1_safe_q[8] & !F1L61);


--F1_safe_q[7] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[7]
--operation mode is arithmetic

F1_safe_q[7]_carry_eqn = F1L41;
F1_safe_q[7]_lut_out = F1_safe_q[7] $ F1_safe_q[7]_carry_eqn;
F1_safe_q[7] = DFFEA(F1_safe_q[7]_lut_out, CLK, VCC, , , , );

--F1L61 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella7~COUT
--operation mode is arithmetic

F1L61 = CARRY(!F1L41 # !F1_safe_q[7]);


--F1_safe_q[6] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[6]
--operation mode is arithmetic

F1_safe_q[6]_carry_eqn = F1L21;
F1_safe_q[6]_lut_out = F1_safe_q[6] $ !F1_safe_q[6]_carry_eqn;
F1_safe_q[6] = DFFEA(F1_safe_q[6]_lut_out, CLK, VCC, , , , );

--F1L41 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella6~COUT
--operation mode is arithmetic

F1L41 = CARRY(F1_safe_q[6] & !F1L21);


--F1_safe_q[5] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[5]
--operation mode is arithmetic

F1_safe_q[5]_carry_eqn = F1L01;
F1_safe_q[5]_lut_out = F1_safe_q[5] $ F1_safe_q[5]_carry_eqn;
F1_safe_q[5] = DFFEA(F1_safe_q[5]_lut_out, CLK, VCC, , , , );

--F1L21 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella5~COUT
--operation mode is arithmetic

F1L21 = CARRY(!F1L01 # !F1_safe_q[5]);


--F1_safe_q[4] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[4]
--operation mode is arithmetic

F1_safe_q[4]_carry_eqn = F1L8;
F1_safe_q[4]_lut_out = F1_safe_q[4] $ !F1_safe_q[4]_carry_eqn;
F1_safe_q[4] = DFFEA(F1_safe_q[4]_lut_out, CLK, VCC, , , , );

--F1L01 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella4~COUT
--operation mode is arithmetic

F1L01 = CARRY(F1_safe_q[4] & !F1L8);


--F1_safe_q[3] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[3]
--operation mode is arithmetic

F1_safe_q[3]_carry_eqn = F1L6;
F1_safe_q[3]_lut_out = F1_safe_q[3] $ F1_safe_q[3]_carry_eqn;
F1_safe_q[3] = DFFEA(F1_safe_q[3]_lut_out, CLK, VCC, , , , );

--F1L8 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

F1L8 = CARRY(!F1L6 # !F1_safe_q[3]);


--F1_safe_q[2] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[2]
--operation mode is arithmetic

F1_safe_q[2]_carry_eqn = F1L4;
F1_safe_q[2]_lut_out = F1_safe_q[2] $ !F1_safe_q[2]_carry_eqn;
F1_safe_q[2] = DFFEA(F1_safe_q[2]_lut_out, CLK, VCC, , , , );

--F1L6 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F1L6 = CARRY(F1_safe_q[2] & !F1L4);


--F1_safe_q[1] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1]
--operation mode is arithmetic

F1_safe_q[1]_carry_eqn = F1L2;
F1_safe_q[1]_lut_out = F1_safe_q[1] $ F1_safe_q[1]_carry_eqn;
F1_safe_q[1] = DFFEA(F1_safe_q[1]_lut_out, CLK, VCC, , , , );

--F1L4 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F1L4 = CARRY(!F1L2 # !F1_safe_q[1]);


--F1_safe_q[0] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[0]
--operation mode is arithmetic

F1_safe_q[0]_lut_out = !F1_safe_q[0];
F1_safe_q[0] = DFFEA(F1_safe_q[0]_lut_out, CLK, VCC, , , , );

--F1L2 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F1L2 = CARRY(F1_safe_q[0]);


--NB1_q_a[7] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[7]_PORT_A_data_in = DIN[7];
NB1_q_a[7]_PORT_A_data_in_reg = DFFE(NB1_q_a[7]_PORT_A_data_in, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_data_in = PB1_ram_rom_data_reg[7];
NB1_q_a[7]_PORT_B_data_in_reg = DFFE(NB1_q_a[7]_PORT_B_data_in, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[7]_PORT_A_address_reg = DFFE(NB1_q_a[7]_PORT_A_address, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[7]_PORT_B_address_reg = DFFE(NB1_q_a[7]_PORT_B_address, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_write_enable = KEY1;
NB1_q_a[7]_PORT_A_write_enable_reg = DFFE(NB1_q_a[7]_PORT_A_write_enable, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_write_enable = PB1L33;
NB1_q_a[7]_PORT_B_write_enable_reg = DFFE(NB1_q_a[7]_PORT_B_write_enable, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_clock_0 = CLK;
NB1_q_a[7]_clock_1 = A1L51;
NB1_q_a[7]_PORT_A_data_out = MEMORY(NB1_q_a[7]_PORT_A_data_in_reg, NB1_q_a[7]_PORT_B_data_in_reg, NB1_q_a[7]_PORT_A_address_reg, NB1_q_a[7]_PORT_B_address_reg, NB1_q_a[7]_PORT_A_write_enable_reg, NB1_q_a[7]_PORT_B_write_enable_reg, , , NB1_q_a[7]_clock_0, NB1_q_a[7]_clock_1, , , , );
NB1_q_a[7] = NB1_q_a[7]_PORT_A_data_out[0];

--NB1_q_b[7] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[7]
NB1_q_b[7]_PORT_A_data_in = DIN[7];
NB1_q_b[7]_PORT_A_data_in_reg = DFFE(NB1_q_b[7]_PORT_A_data_in, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_data_in = PB1_ram_rom_data_reg[7];
NB1_q_b[7]_PORT_B_data_in_reg = DFFE(NB1_q_b[7]_PORT_B_data_in, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[7]_PORT_A_address_reg = DFFE(NB1_q_b[7]_PORT_A_address, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = KEY1;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L33;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = CLK;
NB1_q_b[7]_clock_1 = A1L51;
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[7] = NB1_q_b[7]_PORT_B_data_out[0];


--NB1_q_a[6] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[6]_PORT_A_data_in = DIN[6];
NB1_q_a[6]_PORT_A_data_in_reg = DFFE(NB1_q_a[6]_PORT_A_data_in, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_data_in = PB1_ram_rom_data_reg[6];
NB1_q_a[6]_PORT_B_data_in_reg = DFFE(NB1_q_a[6]_PORT_B_data_in, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[6]_PORT_A_address_reg = DFFE(NB1_q_a[6]_PORT_A_address, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[6]_PORT_B_address_reg = DFFE(NB1_q_a[6]_PORT_B_address, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_write_enable = KEY1;
NB1_q_a[6]_PORT_A_write_enable_reg = DFFE(NB1_q_a[6]_PORT_A_write_enable, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_write_enable = PB1L33;
NB1_q_a[6]_PORT_B_write_enable_reg = DFFE(NB1_q_a[6]_PORT_B_write_enable, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_clock_0 = CLK;
NB1_q_a[6]_clock_1 = A1L51;
NB1_q_a[6]_PORT_A_data_out = MEMORY(NB1_q_a[6]_PORT_A_data_in_reg, NB1_q_a[6]_PORT_B_data_in_reg, NB1_q_a[6]_PORT_A_address_reg, NB1_q_a[6]_PORT_B_address_reg, NB1_q_a[6]_PORT_A_write_enable_reg, NB1_q_a[6]_PORT_B_write_enable_reg, , , NB1_q_a[6]_clock_0, NB1_q_a[6]_clock_1, , , , );
NB1_q_a[6] = NB1_q_a[6]_PORT_A_data_out[0];

--NB1_q_b[6] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[6]
NB1_q_b[6]_PORT_A_data_in = DIN[6];
NB1_q_b[6]_PORT_A_data_in_reg = DFFE(NB1_q_b[6]_PORT_A_data_in, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_data_in = PB1_ram_rom_data_reg[6];
NB1_q_b[6]_PORT_B_data_in_reg = DFFE(NB1_q_b[6]_PORT_B_data_in, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[6]_PORT_A_address_reg = DFFE(NB1_q_b[6]_PORT_A_address, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[6]_PORT_B_address_reg = DFFE(NB1_q_b[6]_PORT_B_address, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_write_enable = KEY1;
NB1_q_b[6]_PORT_A_write_enable_reg = DFFE(NB1_q_b[6]_PORT_A_write_enable, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_write_enable = PB1L33;
NB1_q_b[6]_PORT_B_write_enable_reg = DFFE(NB1_q_b[6]_PORT_B_write_enable, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_clock_0 = CLK;
NB1_q_b[6]_clock_1 = A1L51;
NB1_q_b[6]_PORT_B_data_out = MEMORY(NB1_q_b[6]_PORT_A_data_in_reg, NB1_q_b[6]_PORT_B_data_in_reg, NB1_q_b[6]_PORT_A_address_reg, NB1_q_b[6]_PORT_B_address_reg, NB1_q_b[6]_PORT_A_write_enable_reg, NB1_q_b[6]_PORT_B_write_enable_reg, , , NB1_q_b[6]_clock_0, NB1_q_b[6]_clock_1, , , , );
NB1_q_b[6] = NB1_q_b[6]_PORT_B_data_out[0];


--NB1_q_a[5] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[5]_PORT_A_data_in = DIN[5];
NB1_q_a[5]_PORT_A_data_in_reg = DFFE(NB1_q_a[5]_PORT_A_data_in, NB1_q_a[5]_clock_0, , , );
NB1_q_a[5]_PORT_B_data_in = PB1_ram_rom_data_reg[5];
NB1_q_a[5]_PORT_B_data_in_reg = DFFE(NB1_q_a[5]_PORT_B_data_in, NB1_q_a[5]_clock_1, , , );
NB1_q_a[5]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[5]_PORT_A_address_reg = DFFE(NB1_q_a[5]_PORT_A_address, NB1_q_a[5]_clock_0, , , );
NB1_q_a[5]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[5]_PORT_B_address_reg = DFFE(NB1_q_a[5]_PORT_B_address, NB1_q_a[5]_clock_1, , , );
NB1_q_a[5]_PORT_A_write_enable = KEY1;
NB1_q_a[5]_PORT_A_write_enable_reg = DFFE(NB1_q_a[5]_PORT_A_write_enable, NB1_q_a[5]_clock_0, , , );
NB1_q_a[5]_PORT_B_write_enable = PB1L33;
NB1_q_a[5]_PORT_B_write_enable_reg = DFFE(NB1_q_a[5]_PORT_B_write_enable, NB1_q_a[5]_clock_1, , , );
NB1_q_a[5]_clock_0 = CLK;
NB1_q_a[5]_clock_1 = A1L51;
NB1_q_a[5]_PORT_A_data_out = MEMORY(NB1_q_a[5]_PORT_A_data_in_reg, NB1_q_a[5]_PORT_B_data_in_reg, NB1_q_a[5]_PORT_A_address_reg, NB1_q_a[5]_PORT_B_address_reg, NB1_q_a[5]_PORT_A_write_enable_reg, NB1_q_a[5]_PORT_B_write_enable_reg, , , NB1_q_a[5]_clock_0, NB1_q_a[5]_clock_1, , , , );
NB1_q_a[5] = NB1_q_a[5]_PORT_A_data_out[0];

--NB1_q_b[5] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[5]
NB1_q_b[5]_PORT_A_data_in = DIN[5];
NB1_q_b[5]_PORT_A_data_in_reg = DFFE(NB1_q_b[5]_PORT_A_data_in, NB1_q_b[5]_clock_0, , , );
NB1_q_b[5]_PORT_B_data_in = PB1_ram_rom_data_reg[5];
NB1_q_b[5]_PORT_B_data_in_reg = DFFE(NB1_q_b[5]_PORT_B_data_in, NB1_q_b[5]_clock_1, , , );
NB1_q_b[5]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[5]_PORT_A_address_reg = DFFE(NB1_q_b[5]_PORT_A_address, NB1_q_b[5]_clock_0, , , );
NB1_q_b[5]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[5]_PORT_B_address_reg = DFFE(NB1_q_b[5]_PORT_B_address, NB1_q_b[5]_clock_1, , , );
NB1_q_b[5]_PORT_A_write_enable = KEY1;
NB1_q_b[5]_PORT_A_write_enable_reg = DFFE(NB1_q_b[5]_PORT_A_write_enable, NB1_q_b[5]_clock_0, , , );
NB1_q_b[5]_PORT_B_write_enable = PB1L33;
NB1_q_b[5]_PORT_B_write_enable_reg = DFFE(NB1_q_b[5]_PORT_B_write_enable, NB1_q_b[5]_clock_1, , , );
NB1_q_b[5]_clock_0 = CLK;
NB1_q_b[5]_clock_1 = A1L51;
NB1_q_b[5]_PORT_B_data_out = MEMORY(NB1_q_b[5]_PORT_A_data_in_reg, NB1_q_b[5]_PORT_B_data_in_reg, NB1_q_b[5]_PORT_A_address_reg, NB1_q_b[5]_PORT_B_address_reg, NB1_q_b[5]_PORT_A_write_enable_reg, NB1_q_b[5]_PORT_B_write_enable_reg, , , NB1_q_b[5]_clock_0, NB1_q_b[5]_clock_1, , , , );
NB1_q_b[5] = NB1_q_b[5]_PORT_B_data_out[0];


--NB1_q_a[4] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[4]_PORT_A_data_in = DIN[4];
NB1_q_a[4]_PORT_A_data_in_reg = DFFE(NB1_q_a[4]_PORT_A_data_in, NB1_q_a[4]_clock_0, , , );
NB1_q_a[4]_PORT_B_data_in = PB1_ram_rom_data_reg[4];
NB1_q_a[4]_PORT_B_data_in_reg = DFFE(NB1_q_a[4]_PORT_B_data_in, NB1_q_a[4]_clock_1, , , );
NB1_q_a[4]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[4]_PORT_A_address_reg = DFFE(NB1_q_a[4]_PORT_A_address, NB1_q_a[4]_clock_0, , , );
NB1_q_a[4]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[4]_PORT_B_address_reg = DFFE(NB1_q_a[4]_PORT_B_address, NB1_q_a[4]_clock_1, , , );
NB1_q_a[4]_PORT_A_write_enable = KEY1;
NB1_q_a[4]_PORT_A_write_enable_reg = DFFE(NB1_q_a[4]_PORT_A_write_enable, NB1_q_a[4]_clock_0, , , );
NB1_q_a[4]_PORT_B_write_enable = PB1L33;
NB1_q_a[4]_PORT_B_write_enable_reg = DFFE(NB1_q_a[4]_PORT_B_write_enable, NB1_q_a[4]_clock_1, , , );
NB1_q_a[4]_clock_0 = CLK;
NB1_q_a[4]_clock_1 = A1L51;
NB1_q_a[4]_PORT_A_data_out = MEMORY(NB1_q_a[4]_PORT_A_data_in_reg, NB1_q_a[4]_PORT_B_data_in_reg, NB1_q_a[4]_PORT_A_address_reg, NB1_q_a[4]_PORT_B_address_reg, NB1_q_a[4]_PORT_A_write_enable_reg, NB1_q_a[4]_PORT_B_write_enable_reg, , , NB1_q_a[4]_clock_0, NB1_q_a[4]_clock_1, , , , );
NB1_q_a[4] = NB1_q_a[4]_PORT_A_data_out[0];

--NB1_q_b[4] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[4]
NB1_q_b[4]_PORT_A_data_in = DIN[4];
NB1_q_b[4]_PORT_A_data_in_reg = DFFE(NB1_q_b[4]_PORT_A_data_in, NB1_q_b[4]_clock_0, , , );
NB1_q_b[4]_PORT_B_data_in = PB1_ram_rom_data_reg[4];