music_simple_beep.tcl

基于FPGA的VHDL编程实现各种音频信号

# Created by Libero Project Manager 8.0.3.7
# Fri Feb 22 12:57:17 2008

# (NEW DESIGN)

# create a new design
new_design -name "music_simple_beep" -family "Fusion"
set_device -die "AFS600" -package "256 FBGA"

# set default back-annotation base-name
set_defvar "BA_NAME" "music_simple_beep_ba"

# set working directory
set_defvar "DESDIR" "F:/Actel_prj/myprj/simple_beep/designer/impl1"

# set back-annotation output directory
set_defvar "BA_DIR" "F:/Actel_prj/myprj/simple_beep/designer/impl1"

# enable the export back-annotation netlist
set_defvar "BA_NETLIST_ALSO" "1"

# set EDIF options
set_defvar "EDNINFLAVOR" "GENERIC"

# set HDL options
set_defvar "NETLIST_NAMING_STYLE" "VERILOG"

# setup status report options
set_defvar "EXPORT_STATUS_REPORT" "1"
set_defvar "EXPORT_STATUS_REPORT_FILENAME" "music_simple_beep.rpt"

# legacy audit-mode flags (left here for historical reasons)
set_defvar "AUDIT_NETLIST_FILE" "1"
set_defvar "AUDIT_DCF_FILE" "1"
set_defvar "AUDIT_PIN_FILE" "1"
set_defvar "AUDIT_ADL_FILE" "1"

# import of input files
import_source  \
-format "edif" -edif_flavor "GENERIC" -netlist_naming "VERILOG" {../../synthesis/music_simple_beep.edn} \
-format "sdc"  {..\..\synthesis\music_simple_beep_sdc.sdc}

# save the design database
save_design {music_simple_beep.adb}

show_device_selection_wizard