box.fit.eqn

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。

--M5_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] at LC_X26_Y6_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M5_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, HB1_state[0], GND, HB1_state[11]);


--M5_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] at LC_X26_Y6_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M5_dffs[2] = AMPP_FUNCTION(A1L5, M5_dffs[3], HB1_state[0], GND, HB1_state[11]);


--M5_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5] at LC_X26_Y6_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M5_dffs[5] = AMPP_FUNCTION(A1L5, M5_dffs[6], HB1_state[0], GND, HB1_state[11]);


--M5_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4] at LC_X26_Y6_N2
--operation mode is normal

M5_dffs[4] = AMPP_FUNCTION(A1L5, M5_dffs[5], HB1_state[0], HB1_state[11]);


--C1L7 is sld_hub:sld_hub_inst|Equal~183 at LC_X26_Y6_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1L7 = AMPP_FUNCTION(M5_dffs[5], M5_dffs[2], M5_dffs[4]);

--M5_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3] at LC_X26_Y6_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M5_dffs[3] = AMPP_FUNCTION(A1L5, M5_dffs[4], HB1_state[0], GND, HB1_state[11]);


--M5_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] at LC_X26_Y6_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

M5_dffs[0] = AMPP_FUNCTION(A1L5, M5_dffs[1], HB1_state[0], GND, HB1_state[11]);


--JB1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] at LC_X26_Y7_N1
--operation mode is normal

JB1_dffe1a[1] = AMPP_FUNCTION(A1L5, FB3_Q[1], FB3_Q[2], FB3_Q[3], C1L31, C1_CLRN_SIGNAL, C1L5);


--HB1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] at LC_X27_Y8_N7
--operation mode is normal

HB1_state[8] = AMPP_FUNCTION(A1L5, HB1_state[5], HB1_state[7], VCC, !A1L7);


--C1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28 at LC_X24_Y7_N0
--operation mode is normal

C1L1 = AMPP_FUNCTION(HB1_state[8], JB1_dffe1a[1], C1_OK_TO_UPDATE_IR_Q, JB1_dffe1a[2]);


--A1L142 is Q1[0]~504 at LC_X16_Y7_N9
--operation mode is normal

A1L142 = Q1[6] & (Q1[7] $ DS1 # !DS0) # !Q1[6] & (DS0 # Q1[7] $ DS1);


--FB5_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] at LC_X20_Y8_N8
--operation mode is normal

FB5_Q[3] = AMPP_FUNCTION(A1L5, FB7_Q[3], FB2_Q[0], FB3_Q[3], C1_CLRN_SIGNAL, C1L25);


--MB1_ram_rom_data_shift_cntr_reg[1] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] at LC_X20_Y7_N7
--operation mode is arithmetic

MB1_ram_rom_data_shift_cntr_reg[1] = AMPP_FUNCTION(A1L5, MB1_ram_rom_data_shift_cntr_reg[1], !FB5_Q[3], MB1L4, MB1L53, MB1L54);

--MB1L56 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]~51 at LC_X20_Y7_N7
--operation mode is arithmetic

MB1L56 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[1], MB1L53);

--MB1L57 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]~51COUT1 at LC_X20_Y7_N7
--operation mode is arithmetic

MB1L57 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[1], MB1L54);


--FB5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] at LC_X21_Y7_N0
--operation mode is normal

FB5_Q[1] = AMPP_FUNCTION(A1L5, FB3_Q[1], FB2_Q[0], FB7_Q[1], C1_CLRN_SIGNAL, C1L25);


--MB1_ram_rom_data_shift_cntr_reg[0] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] at LC_X20_Y7_N6
--operation mode is arithmetic

MB1_ram_rom_data_shift_cntr_reg[0] = AMPP_FUNCTION(A1L5, MB1_ram_rom_data_shift_cntr_reg[0], MB1L14, !FB5_Q[3], MB1L4);

--MB1L53 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~55 at LC_X20_Y7_N6
--operation mode is arithmetic

MB1L53 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[0], MB1L14);

--MB1L54 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~55COUT1_67 at LC_X20_Y7_N6
--operation mode is arithmetic

MB1L54 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[0], MB1L14);


--MB1_ram_rom_data_shift_cntr_reg[2] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] at LC_X20_Y7_N8
--operation mode is arithmetic

MB1_ram_rom_data_shift_cntr_reg[2] = AMPP_FUNCTION(A1L5, MB1_ram_rom_data_shift_cntr_reg[2], !FB5_Q[3], MB1L4, MB1L56, MB1L57);

--MB1L59 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]~59 at LC_X20_Y7_N8
--operation mode is arithmetic

MB1L59 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[2], MB1L56);

--MB1L60 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]~59COUT1_68 at LC_X20_Y7_N8
--operation mode is arithmetic

MB1L60 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[2], MB1L57);


--MB1_ram_rom_data_shift_cntr_reg[3] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] at LC_X20_Y7_N9
--operation mode is normal

MB1_ram_rom_data_shift_cntr_reg[3] = AMPP_FUNCTION(A1L5, MB1_ram_rom_data_shift_cntr_reg[3], !FB5_Q[3], MB1L4, MB1L59, MB1L60);


--MB1L3 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|Equal~44 at LC_X21_Y7_N2
--operation mode is normal

MB1L3 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[3], MB1_ram_rom_data_shift_cntr_reg[2], MB1_ram_rom_data_shift_cntr_reg[0]);


--MB1L13 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 at LC_X21_Y7_N7
--operation mode is normal

MB1L13 = AMPP_FUNCTION(FB5_Q[1], MB1_ram_rom_data_shift_cntr_reg[1], MB1L3, FB5_Q[3]);


--FB5L4 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 at LC_X21_Y7_N4
--operation mode is normal

FB5L4 = AMPP_FUNCTION(FB5_Q[1], FB5_Q[2]);


--MB1L50 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]~885 at LC_X21_Y7_N5
--operation mode is normal

MB1L50 = AMPP_FUNCTION(MB1L13, FB5L4, HB1_state[4], MB1L64);


--MB1L63 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~0 at LC_X21_Y7_N9
--operation mode is normal

MB1L63 = AMPP_FUNCTION(FB5_Q[1], MB1L3, MB1_ram_rom_data_shift_cntr_reg[1]);


--MB1_ram_rom_incr_addr is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr at LC_X19_Y8_N7
--operation mode is normal

MB1_ram_rom_incr_addr = AMPP_FUNCTION(HB1_state[8], MB1L64, MB1L63, FB5_Q[2]);


--FB5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] at LC_X21_Y7_N8
--operation mode is normal

FB5_Q[0] = AMPP_FUNCTION(A1L5, FB7_Q[0], FB3_Q[0], FB2_Q[0], C1_CLRN_SIGNAL, C1L25);


--MB1L12 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~12 at LC_X20_Y8_N9
--operation mode is normal

MB1L12 = AMPP_FUNCTION(HB1_state[4], FB5_Q[3], MB1L64);


--next_command.func_set is next_command.func_set at LC_X14_Y13_N9
--operation mode is normal

next_command.func_set_lut_out = state.reset3 # next_command.func_set & (state.hold # state.toggle_e);
next_command.func_set = DFFEAS(next_command.func_set_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--next_command.reset2 is next_command.reset2 at LC_X14_Y13_N0
--operation mode is normal

next_command.reset2_lut_out = state.reset1 & (next_command.reset2 # !state.hold & !state.toggle_e);
next_command.reset2 = DFFEAS(next_command.reset2_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--next_command.reset3 is next_command.reset3 at LC_X14_Y13_N6
--operation mode is normal

next_command.reset3_lut_out = state.reset2 # next_command.reset3 & (state.toggle_e # state.hold);
next_command.reset3 = DFFEAS(next_command.reset3_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--next_command.display_on is next_command.display_on at LC_X14_Y11_N1
--operation mode is normal

next_command.display_on_lut_out = state.display_clear # next_command.display_on & (state.hold # state.toggle_e);
next_command.display_on = DFFEAS(next_command.display_on_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--next_command.display_off is next_command.display_off at LC_X14_Y11_N8
--operation mode is normal

next_command.display_off_lut_out = state.func_set # next_command.display_off & (state.hold # state.toggle_e);
next_command.display_off = DFFEAS(next_command.display_off_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--next_command.display_set is next_command.display_set at LC_X15_Y12_N0
--operation mode is normal

next_command.display_set_lut_out = state.return_home # state.mode_set # next_command.display_set & !A1L164;
next_command.display_set = DFFEAS(next_command.display_set_lut_out, GLOBAL(CLK_400HZ), !GLOBAL(RES), , , , , , );


--A1L164 is Select~2562 at LC_X15_Y13_N8
--operation mode is normal

A1L164 = !state.toggle_e & (!state.hold);


--next_command.display_clear is next_command.display_clear at LC_X14_Y11_N4
--operation mode is normal

next_command.display_clear_lut_out = state.display_off # next_command.display_c