box.tan.qmsg

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] register sld_hub:sld_hub_inst\|hub_tdo 95.13 MHz 10.512 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 95.13 MHz between source register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 10.512 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.995 ns + Longest register register " "Info: + Longest register to register delay is 4.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 1 REG LC_X25_Y8_N5 41 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y8_N5; Fanout = 41; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.797 ns) + CELL(0.292 ns) 2.089 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13 2 COMB LC_X22_Y7_N8 1 " "Info: 2: + IC(1.797 ns) + CELL(0.292 ns) = 2.089 ns; Loc. = LC_X22_Y7_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.089 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.421 ns) + CELL(0.442 ns) 2.952 ns sld_hub:sld_hub_inst\|hub_tdo~811 3 COMB LC_X22_Y7_N4 1 " "Info: 3: + IC(0.421 ns) + CELL(0.442 ns) = 2.952 ns; Loc. = LC_X22_Y7_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~811'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "0.863 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~811 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.421 ns) + CELL(0.442 ns) 3.815 ns sld_hub:sld_hub_inst\|hub_tdo~813 4 COMB LC_X22_Y7_N1 1 " "Info: 4: + IC(0.421 ns) + CELL(0.442 ns) = 3.815 ns; Loc. = LC_X22_Y7_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~813'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "0.863 ns" { sld_hub:sld_hub_inst|hub_tdo~811 sld_hub:sld_hub_inst|hub_tdo~813 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.738 ns) 4.995 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LC_X22_Y7_N9 1 " "Info: 5: + IC(0.442 ns) + CELL(0.738 ns) = 4.995 ns; Loc. = LC_X22_Y7_N9; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "1.180 ns" { sld_hub:sld_hub_inst|hub_tdo~813 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.914 ns ( 38.32 % ) " "Info: Total cell delay = 1.914 ns ( 38.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.081 ns ( 61.68 % ) " "Info: Total interconnect delay = 3.081 ns ( 61.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "4.995 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~811 sld_hub:sld_hub_inst|hub_tdo~813 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "4.995 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~811 sld_hub:sld_hub_inst|hub_tdo~813 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.797ns 0.421ns 0.421ns 0.442ns } { 0.000ns 0.292ns 0.442ns 0.442ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.281 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.281 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 311 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 311; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.570 ns) + CELL(0.711 ns) 5.281 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X22_Y7_N9 1 " "Info: 2: + IC(4.570 ns) + CELL(0.711 ns) = 5.281 ns; Loc. = LC_X22_Y7_N9; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.46 % ) " "Info: Total cell delay = 0.711 ns ( 13.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.570 ns ( 86.54 % ) " "Info: Total interconnect delay = 4.570 ns ( 86.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.570ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.281 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.281 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 311 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 311; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.570 ns) + CELL(0.711 ns) 5.281 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 2 REG LC_X25_Y8_N5 41 " "Info: 2: + IC(4.570 ns) + CELL(0.711 ns) = 5.281 ns; Loc. = LC_X25_Y8_N5; Fanout = 41; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.46 % ) " "Info: Total cell delay = 0.711 ns ( 13.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.570 ns ( 86.54 % ) " "Info: Total interconnect delay = 4.570 ns ( 86.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.570ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.570ns } { 0.000ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.570ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1144 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1144 -1 0 } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "4.995 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~811 sld_hub:sld_hub_inst|hub_tdo~813 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "4.995 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~811 sld_hub:sld_hub_inst|hub_tdo~813 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.797ns 0.421ns 0.421ns 0.442ns } { 0.000ns 0.292ns 0.442ns 0.442ns 0.738ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.570ns } { 0.000ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "5.281 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.570ns } { 0.000ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "auto_stp_external_clock_0 register sld_signaltap:BOX\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_0id:auto_generated\|safe_q\[1\] memory sld_signaltap:BOX\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_tjb2:auto_generated\|ram_block1a0~porta_datain_reg3 130.36 MHz 7.671 ns Internal " "Info: Clock \"auto_stp_external_clock_0\" has Internal fmax of 130.36 MHz between source register \"sld_signaltap:BOX\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_0id:auto_generated\|safe_q\[1\]\" and destination memory \"sld_signaltap:BOX\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_tjb2:auto_generated\|ram_block1a0~porta_datain_reg3\" (period= 7.671 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.365 ns + Longest register memory " "Info: + Longest register to memory delay is 7.365 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:BOX\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_0id:auto_generated\|safe_q\[1\] 1 REG LC_X20_Y12_N6 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y12_N6; Fanout = 9; REG Node = 'sld_signaltap:BOX\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_0id:auto_generated\|safe_q\[1\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { sld_signaltap:BOX|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_0id:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_0id.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/cntr_0id.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.575 ns) 1.102 ns sld_signaltap:BOX\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_0id:auto_generated\|counter_cella1~COUTCOUT1_1 2 COMB LC_X20_Y12_N6 2 " "Info: 2: + IC(0.527 ns) + CELL(0.575 ns) = 1.102 ns; Loc. = LC_X20_Y12_N6; Fanout = 2; COMB Node = 'sld_signaltap:BOX\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_0id:auto_generated\|counter_cella1~COUTCOUT1_1'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "1.102 ns" { sld_signaltap:BOX|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_0id:auto_generated|safe_q[1] sld_signaltap:BOX|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_0id:auto_generated|counter_cella1~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_0id.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/cntr_0id.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.182 ns sld_signaltap:BOX\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_c