box.tan.qmsg

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLLU:u2\|altpll:altpll_component\|_clk0 memory allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_datain_reg0 memory allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_memory_reg0 4.923 ns " "Info: Slack time is 4.923 ns for clock \"PLLU:u2\|altpll:altpll_component\|_clk0\" between source memory \"allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_datain_reg0\" and destination memory \"allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_memory_reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "197.01 MHz 5.076 ns " "Info: Fmax is 197.01 MHz (period= 5.076 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.242 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 9.242 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "9.999 ns + " "Info: + Setup relationship between source and destination is 9.999 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 8.114 ns " "Info: + Latch edge is 8.114 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLLU:u2\|altpll:altpll_component\|_clk0 9.999 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"PLLU:u2\|altpll:altpll_component\|_clk0\" is 9.999 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLLU:u2\|altpll:altpll_component\|_clk0 9.999 ns -1.885 ns  50 " "Info: Clock period of Source clock \"PLLU:u2\|altpll:altpll_component\|_clk0\" is 9.999 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns + Largest " "Info: + Largest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLLU:u2\|altpll:altpll_component\|_clk0 destination 2.350 ns + Shortest memory " "Info: + Shortest clock path from clock \"PLLU:u2\|altpll:altpll_component\|_clk0\" to destination memory is 2.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLLU:u2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 33; CLK Node = 'PLLU:u2\|altpll:altpll_component\|_clk0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { PLLU:u2|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.708 ns) 2.350 ns allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_memory_reg0 2 MEM M4K_X17_Y8 0 " "Info: 2: + IC(1.642 ns) + CELL(0.708 ns) = 2.350 ns; Loc. = M4K_X17_Y8; Fanout = 0; MEM Node = 'allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_memory_reg0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_sfa2.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/altsyncram_sfa2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.708 ns ( 30.13 % ) " "Info: Total cell delay = 0.708 ns ( 30.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns ( 69.87 % ) " "Info: Total interconnect delay = 1.642 ns ( 69.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLLU:u2\|altpll:altpll_component\|_clk0 source 2.364 ns - Longest memory " "Info: - Longest clock path from clock \"PLLU:u2\|altpll:altpll_component\|_clk0\" to source memory is 2.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLLU:u2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 33; CLK Node = 'PLLU:u2\|altpll:altpll_component\|_clk0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { PLLU:u2|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.722 ns) 2.364 ns allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_datain_reg0 2 MEM M4K_X17_Y8 1 " "Info: 2: + IC(1.642 ns) + CELL(0.722 ns) = 2.364 ns; Loc. = M4K_X17_Y8; Fanout = 1; MEM Node = 'allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_datain_reg0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_sfa2.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/altsyncram_sfa2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 30.54 % ) " "Info: Total cell delay = 0.722 ns ( 30.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns ( 69.46 % ) " "Info: Total interconnect delay = 1.642 ns ( 69.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.708ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_sfa2.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/altsyncram_sfa2.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_sfa2.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/altsyncram_sfa2.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.708ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns - Longest memory memory " "Info: - Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_datain_reg0 1 MEM M4K_X17_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y8; Fanout = 1; MEM Node = 'allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_datain_reg0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_sfa2.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/altsyncram_sfa2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_memory_reg0 2 MEM M4K_X17_Y8 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y8; Fanout = 0; MEM Node = 'allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_memory_reg0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "4.319 ns" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_sfa2.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/altsyncram_sfa2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "4.319 ns" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "4.319 ns" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.350 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.708ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.364 ns" { PLLU:u2|altpll:altpll_component|_clk0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "4.319 ns" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "4.319 ns" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK register CLK_COUNT_400HZ\[8\] register CLK_COUNT_400HZ\[5\] 13.463 ns " "Info: Slack time is 13.463 ns for clock \"CLK\" between source register \"CLK_COUNT_400HZ\[8\]\" and destination register \"CLK_COUNT_400HZ\[5\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "135.69 MHz 7.37 ns " "Info: Fmax is 135.69 MHz (period= 7.37 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "20.572 ns + Largest register register " "Info: + Largest register to register requirement is 20.572 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.833 ns + " "Info: + Setup relationship between source and destination is 20.833 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.833 ns " "Info: + Latch edge is 20.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK 20.833 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK\" is 20.833 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK 20.833 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK\" is 20.833 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.926 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'CLK'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { CLK } "NODE_NAME" } "" } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.746 ns) + CELL(0.711 ns) 2.926 ns CLK_COUNT_400HZ\[5\] 2 REG LC_X15_Y11_N5 4 " "Info: 2: + IC(0.746 ns) + CELL(0.711 ns) = 2.926 ns; Loc. = LC_X15_Y11_N5; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[5\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "1.457 ns" { CLK CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.50 % ) " "Info: Total cell delay = 2.180 ns ( 74.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.746 ns ( 25.50 % ) " "Info: Total interconnect delay = 0.746 ns ( 25.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.926 ns" { CLK CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.926 ns" { CLK CLK~out0 CLK_COUNT_400HZ[5] } { 0.000ns 0.000ns 0.746ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.926 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'CLK'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { CLK } "NODE_NAME" } "" } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.746 ns) + CELL(0.711 ns) 2.926 ns CLK_COUNT_400HZ\[8\] 2 REG LC_X15_Y11_N8 4 " "Info: 2: + IC(0.746 ns) + CELL(0.711 ns) = 2.926 ns; Loc. = LC_X15_Y11_N8; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[8\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "1.457 ns" { CLK CLK_COUNT_400HZ[8] } "NODE_NAME" } "" } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.50 % ) " "Info: Total cell delay = 2.180 ns ( 74.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.746 ns ( 25.50 % ) " "Info: Total interconnect delay = 0.746 ns ( 25.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.926 ns" { CLK CLK_COUNT_400HZ[8] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.926 ns" { CLK CLK~out0 CLK_COUNT_400HZ[8] } { 0.000ns 0.000ns 0.746ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.926 ns" { CLK CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.926 ns" { CLK CLK~out0 CLK_COUNT_400HZ[5] } { 0.000ns 0.000ns 0.746ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.926 ns" { CLK CLK_COUNT_400HZ[8] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.926 ns" { CLK CLK~out0 CLK_COUNT_400HZ[8] } { 0.000ns 0.000ns 0.746ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 69 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 69 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.926 ns" { CLK CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.926 ns" { CLK CLK~out0 CLK_COUNT_400HZ[5] } { 0.000ns 0.000ns 0.746ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.926 ns" { CLK CLK_COUNT_400HZ[8] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.926 ns" { CLK CLK~out0 CLK_COUNT_400HZ[8] } { 0.000ns 0.000ns 0.746ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.109 ns - Longest register register " "Info: - Longest register to register delay is 7.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_COUNT_400HZ\[8\] 1 REG LC_X15_Y11_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y11_N8; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[8\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { CLK_COUNT_400HZ[8] } "NODE_NAME" } "" } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.655 ns) + CELL(0.442 ns) 2.097 ns LessThan~847 2 COMB LC_X16_Y10_N7 1 " "Info: 2: + IC(1.655 ns) + CELL(0.442 ns) = 2.097 ns; Loc. = LC_X16_Y10_N7; Fanout = 1; COMB Node = 'LessThan~847'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.097 ns" { CLK_COUNT_400HZ[8] LessThan~847 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.590 ns) 3.121 ns LessThan~848 3 COMB LC_X16_Y10_N4 1 " "Info: 3: + IC(0.434 ns) + CELL(0.590 ns) = 3.121 ns; Loc. = LC_X16_Y10_N4; Fanout = 1; COMB Node = 'LessThan~848'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "1.024 ns" { LessThan~847 LessThan~848 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.405 ns) + CELL(0.442 ns) 3.968 ns LessThan~850 4 COMB LC_X16_Y10_N9 2 " "Info: 4: + IC(0.405 ns) + CELL(0.442 ns) = 3.968 ns; Loc. = LC_X16_Y10_N9; Fanout = 2; COMB Node = 'LessThan~850'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "0.847 ns" { LessThan~848 LessThan~850 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.292 ns) 4.716 ns CLK_COUNT_400HZ\[19\]~396 5 COMB LC_X16_Y10_N2 20 " "Info: 5: + IC(0.456 ns) + CELL(0.292 ns) = 4.716 ns; Loc. = LC_X16_Y10_N2; Fanout = 20; COMB Node = 'CLK_COUNT_400HZ\[19\]~396'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "0.748 ns" { LessThan~850 CLK_COUNT_400HZ[19]~396 } "NODE_NAME" } "" } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.281 ns) + CELL(1.112 ns) 7.109 ns CLK_COUNT_400HZ\[5\] 6 REG LC_X15_Y11_N5 4 " "Info: 6: + IC(1.281 ns) + CELL(1.112 ns) = 7.109 ns; Loc. = LC_X15_Y11_N5; Fanout = 4; REG Node = 'CLK_COUNT_400HZ\[5\]'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.393 ns" { CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.878 ns ( 40.48 % ) " "Info: Total cell delay = 2.878 ns ( 40.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.231 ns ( 59.52 % ) " "Info: Total interconnect delay = 4.231 ns ( 59.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "7.109 ns" { CLK_COUNT_400HZ[8] LessThan~847 LessThan~848 LessThan~850 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "7.109 ns" { CLK_COUNT_400HZ[8] LessThan~847 LessThan~848 LessThan~850 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } { 0.000ns 1.655ns 0.434ns 0.405ns 0.456ns 1.281ns } { 0.000ns 0.442ns 0.590ns 0.442ns 0.292ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.926 ns" { CLK CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.926 ns" { CLK CLK~out0 CLK_COUNT_400HZ[5] } { 0.000ns 0.000ns 0.746ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "2.926 ns" { CLK CLK_COUNT_400HZ[8] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "2.926 ns" { CLK CLK~out0 CLK_COUNT_400HZ[8] } { 0.000ns 0.000ns 0.746ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "7.109 ns" { CLK_COUNT_400HZ[8] LessThan~847 LessThan~848 LessThan~850 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/aa/altera/quartus51/bin/Technology_Viewer.qrui" "7.109 ns" { CLK_COUNT_400HZ[8] LessThan~847 LessThan~848 LessThan~850 CLK_COUNT_400HZ[19]~396 CLK_COUNT_400HZ[5] } { 0.000ns 1.655ns 0.434ns 0.405ns 0.456ns 1.281ns } { 0.000ns 0.442ns 0.590ns 0.442ns 0.292ns 1.112ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}