📄 box.tan.qmsg
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{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" { } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "auto_stp_external_clock_0 " "Info: Assuming node \"auto_stp_external_clock_0\" is an undefined clock" { } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "auto_stp_external_clock_0" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_400HZ " "Info: Detected ripple clock \"CLK_400HZ\" as buffer" { } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 47 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_400HZ" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
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