box.fit.qmsg

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.319 ns memory memory " "Info: Estimated most critical path is memory to memory delay of 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_datain_reg0 1 MEM M4K_X17_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y8; Fanout = 1; MEM Node = 'allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_datain_reg0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_sfa2.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/altsyncram_sfa2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_memory_reg0 2 MEM M4K_X17_Y8 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y8; Fanout = 0; MEM Node = 'allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|altsyncram_sfa2:altsyncram1\|ram_block3a0~porta_memory_reg0'" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "4.319 ns" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_sfa2.tdf" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/altsyncram_sfa2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "4.319 ns" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0 allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 7 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 7%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLRN_SIGNAL " "Info: Node sld_hub:sld_hub_inst\|CLRN_SIGNAL uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[8\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[8\] -- routed using non-global resources" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[8\]" } } } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out " "Info: Port clear -- assigned as a global for destination node allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out -- routed using non-global resources" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "allwave:u1\|altsyncram:altsyncram_component\|altsyncram_dpu:auto_generated\|sld_mod_ram_rom:mgl_prim2\|bypass_reg_out" } } } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 183 -1 0 } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]" } } } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\] -- routed using non-global resources" {  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\]" } } } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL } "NODE_NAME" } "" } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLRN_SIGNAL" } } } } { "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { sld_hub:sld_hub_inst|CLRN_SIGNAL } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "8 " "Warning: Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[0\] a permanently enabled " "Info: Pin DATA_BUS\[0\] has a permanently enabled output enable" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[0\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { DATA_BUS[0] } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { DATA_BUS[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[1\] a permanently enabled " "Info: Pin DATA_BUS\[1\] has a permanently enabled output enable" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[1\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { DATA_BUS[1] } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { DATA_BUS[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[2\] a permanently enabled " "Info: Pin DATA_BUS\[2\] has a permanently enabled output enable" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[2\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { DATA_BUS[2] } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { DATA_BUS[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[3\] a permanently enabled " "Info: Pin DATA_BUS\[3\] has a permanently enabled output enable" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[3\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { DATA_BUS[3] } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { DATA_BUS[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[4\] a permanently enabled " "Info: Pin DATA_BUS\[4\] has a permanently enabled output enable" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[4\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { DATA_BUS[4] } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { DATA_BUS[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[5\] a permanently enabled " "Info: Pin DATA_BUS\[5\] has a permanently enabled output enable" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[5\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { DATA_BUS[5] } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { DATA_BUS[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[6\] a permanently enabled " "Info: Pin DATA_BUS\[6\] has a permanently enabled output enable" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[6\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { DATA_BUS[6] } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { DATA_BUS[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DATA_BUS\[7\] a permanently enabled " "Info: Pin DATA_BUS\[7\] has a permanently enabled output enable" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 12 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DATA_BUS\[7\]" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { DATA_BUS[7] } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { DATA_BUS[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_RW GND " "Info: Pin LCD_RW has GND driving its datain port" {  } { { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 11 -1 0 } } { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { LCD_RW } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { LCD_RW } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 24 23:09:02 2007 " "Info: Processing ended: Sun Jun 24 23:09:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}