box.fit.qmsg

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 24 23:08:53 2007 " "Info: Processing started: Sun Jun 24 23:08:53 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off BOX -c BOX " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off BOX -c BOX" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "BOX EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"BOX\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "PLLU:u2\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"PLLU:u2\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLLU:u2\|altpll:altpll_component\|_clk0 25 12 0 0 " "Info: Implementing clock multiplication of 25, clock division of 12, and phase shift of 0 degrees (0 ps) for PLLU:u2\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } } { "PLLU.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/PLLU.vhd" 88 -1 0 } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 377 -1 0 } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "5 28 " "Info: No exact pin location assignment(s) for 5 pins of 28 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { altera_reserved_tdo } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { altera_reserved_tms } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { altera_reserved_tck } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { altera_reserved_tdi } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "auto_stp_external_clock_0 " "Info: Pin auto_stp_external_clock_0 not assigned to an exact location on the device" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "auto_stp_external_clock_0" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { auto_stp_external_clock_0 } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { auto_stp_external_clock_0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "CLK " "Info: Promoted signal \"CLK\" to use global clock" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } { 0 "CLK" } } } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 6 -1 0 } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { CLK } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "PLLU:u2\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"PLLU:u2\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PLLU:u2\|altpll:altpll_component\|_clk0" } { 0 "PLLU:u2\|altpll:altpll_component\|_clk0" } } } } { "BOX.vhd" "" { Text "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.vhd" 377 -1 0 } } { "altpll.tdf" "" { Text "d:/aa/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { PLLU:u2|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { PLLU:u2|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "auto_stp_external_clock_0 Global clock in PIN 28 " "Info: Automatically promoted signal \"auto_stp_external_clock_0\" to use Global clock in PIN 28" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "auto_stp_external_clock_0" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { auto_stp_external_clock_0 } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { auto_stp_external_clock_0 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "d:/aa/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/aa/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/aa/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "BOX" "UNKNOWN" "V1" "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/db/BOX.quartus_db" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" { Floorplan "C:/Documents and Settings/zhao/My Documents/zhao/新建文件夹/BOX.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}