box.hif

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。

C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk0
-1
3
clk0
-1
3
areset
-1
3
inclk1
-1
1
}
# include_file {
d:|altera|quartus51|libraries|megafunctions|aglobal51.inc
c49d61e8168d42962ec885e3e17640c2
d:|altera|quartus51|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
d:|altera|quartus51|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
d:|altera|quartus51|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# end
# entity
altsyncram
# storage
db|BOX.(18).cnf
db|BOX.(18).cnf
# case_insensitive
# source_file
d:|aa|altera|quartus51|libraries|megafunctions|altsyncram.tdf
6d23188b861aaf86e7848b32051ebea
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
allwave.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_dpu
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
d:|aa|altera|quartus51|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
d:|aa|altera|quartus51|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|aa|altera|quartus51|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
d:|aa|altera|quartus51|libraries|megafunctions|aglobal51.inc
c49d61e8168d42962ec885e3e17640c2
d:|aa|altera|quartus51|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
d:|aa|altera|quartus51|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
d:|aa|altera|quartus51|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
d:|aa|altera|quartus51|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
d:|aa|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|aa|altera|quartus51|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
allwave:u1|altsyncram:altsyncram_component
}
# end
# entity
sld_mod_ram_rom
# storage
db|BOX.(19).cnf
db|BOX.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|aa|altera|quartus51|libraries|megafunctions|sld_mod_ram_rom.vhd
c958fec0873e36d747472a38d5139fbe
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
135818752
PARAMETER_DEC
DEF
sld_ip_version
1
PARAMETER_DEC
DEF
sld_ip_minor_version
2
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
8
PARAMETER_UNKNOWN
USR
numwords
256
PARAMETER_UNKNOWN
USR
widthad
8
PARAMETER_UNKNOWN
USR
shift_count_bits
4
PARAMETER_UNKNOWN
USR
cvalue
00000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1380928817
PARAMETER_UNKNOWN
USR
 constraint(address)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2
}
# end
# entity
sld_rom_sr
# storage
db|BOX.(20).cnf
db|BOX.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
d:|aa|altera|quartus51|libraries|megafunctions|sld_rom_sr.vhd
dd9c9d3664071f3cf9eba23cb5af4ac
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
80
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
 constraint(rom_data)
79 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
}
# end
# entity
altpll
# storage
db|BOX.(21).cnf
db|BOX.(21).cnf
# case_insensitive
# source_file
d:|aa|altera|quartus51|libraries|megafunctions|altpll.tdf
57623f25b2431eb0e0c05145e56f2
6
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20833
PARAMETER_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
25
PARAMETER_DEC
USR
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
12
PARAMETER_DEC
USR
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_DEC
USR
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH