box.hier_info

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。

clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
data_b[4] => ram_block3a4.PORTBDATAIN
data_b[5] => ram_block3a5.PORTBDATAIN
data_b[6] => ram_block3a6.PORTBDATAIN
data_b[7] => ram_block3a7.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_a[4] <= ram_block3a4.PORTADATAOUT
q_a[5] <= ram_block3a5.PORTADATAOUT
q_a[6] <= ram_block3a6.PORTADATAOUT
q_a[7] <= ram_block3a7.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE
wren_b => ram_block3a4.PORTBRE
wren_b => ram_block3a5.PORTBRE
wren_b => ram_block3a6.PORTBRE
wren_b => ram_block3a7.PORTBRE


|BOX|allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= enable_write~0.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~15.DATAB
data_read[1] => ram_rom_data_reg~14.DATAB
data_read[2] => ram_rom_data_reg~13.DATAB
data_read[3] => ram_rom_data_reg~12.DATAB
data_read[4] => ram_rom_data_reg~11.DATAB
data_read[5] => ram_rom_data_reg~10.DATAB
data_read[6] => ram_rom_data_reg~9.DATAB
data_read[7] => ram_rom_data_reg~8.DATAB
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_data_reg[7].CLK
raw_tck => ram_rom_data_reg[6].CLK
raw_tck => ram_rom_data_reg[5].CLK
raw_tck => ram_rom_data_reg[4].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[3].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => bypass_reg_out.CLK
raw_tck => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TCK
raw_tck => is_in_use_reg.CLK
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => tck_usr.DATAIN
tdi => ram_rom_addr_reg~8.DATAB
tdi => ram_rom_data_reg~0.DATAB
tdi => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TDI
tdi => bypass_reg_out.DATAIN
usr1 => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.USR1
usr1 => dr_scan.IN0
usr1 => name_gen~0.IN0
jtag_state_cdr => name_gen~1.IN1
jtag_state_sdr => sdr.IN0
jtag_state_sdr => name_gen~1.IN0
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.SHIFT
jtag_state_e1dr => ram_rom_update_write_ena.IN1
jtag_state_udr => udr.IN0
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.UPDATE
jtag_state_uir => ~NO_FANOUT~
clrn => bypass_reg_out.ACLR
clrn => is_in_use_reg.ACLR
ena => dr_scan.IN1
ena => name_gen~0.IN1
ena => bypass_reg_out.ENA
ir_in[0] => ram_rom_addr_reg[6].ACLR
ir_in[0] => ram_rom_addr_reg[5].ACLR
ir_in[0] => ram_rom_addr_reg[4].ACLR
ir_in[0] => ram_rom_addr_reg[3].ACLR
ir_in[0] => ram_rom_addr_reg[2].ACLR
ir_in[0] => ram_rom_addr_reg[1].ACLR
ir_in[0] => ram_rom_addr_reg[0].ACLR
ir_in[0] => process4~0.IN0
ir_in[0] => tdo~1.OUTPUTSELECT
ir_in[0] => is_in_use_reg~1.OUTPUTSELECT
ir_in[0] => ram_rom_addr_reg[7].ACLR
ir_in[1] => process1~0.IN0
ir_in[1] => process1~2.IN1
ir_in[1] => ram_rom_incr_addr~0.IN0
ir_in[2] => process1~2.IN0
ir_in[2] => ram_rom_incr_addr~1.IN0
ir_in[2] => enable_write~0.IN0
ir_in[3] => process0~0.IN1
ir_in[3] => process1~1.IN0
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR
ir_in[3] => process4~1.IN1
ir_in[3] => ram_rom_data_shift_cntr_reg[3].ACLR
ir_in[4] => process4~0.IN1
ir_in[4] => is_in_use_reg~0.OUTPUTSELECT
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE
irq <= <GND>
tdo <= tdo~1.DB_MAX_OUTPUT_PORT_TYPE


|BOX|allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
ROM_DATA[0] => Mux~3.IN131
ROM_DATA[1] => Mux~2.IN131
ROM_DATA[2] => Mux~1.IN131
ROM_DATA[3] => Mux~0.IN131
ROM_DATA[4] => Mux~3.IN127
ROM_DATA[5] => Mux~2.IN127
ROM_DATA[6] => Mux~1.IN127
ROM_DATA[7] => Mux~0.IN127
ROM_DATA[8] => Mux~3.IN123
ROM_DATA[9] => Mux~2.IN123
ROM_DATA[10] => Mux~1.IN123
ROM_DATA[11] => Mux~0.IN123
ROM_DATA[12] => Mux~3.IN119
ROM_DATA[13] => Mux~2.IN119
ROM_DATA[14] => Mux~1.IN119
ROM_DATA[15] => Mux~0.IN119
ROM_DATA[16] => Mux~3.IN115
ROM_DATA[17] => Mux~2.IN115
ROM_DATA[18] => Mux~1.IN115
ROM_DATA[19] => Mux~0.IN115
ROM_DATA[20] => Mux~3.IN111
ROM_DATA[21] => Mux~2.IN111
ROM_DATA[22] => Mux~1.IN111
ROM_DATA[23] => Mux~0.IN111
ROM_DATA[24] => Mux~3.IN107
ROM_DATA[25] => Mux~2.IN107
ROM_DATA[26] => Mux~1.IN107
ROM_DATA[27] => Mux~0.IN107
ROM_DATA[28] => Mux~3.IN103
ROM_DATA[29] => Mux~2.IN103
ROM_DATA[30] => Mux~1.IN103
ROM_DATA[31] => Mux~0.IN103
ROM_DATA[32] => Mux~3.IN99
ROM_DATA[33] => Mux~2.IN99
ROM_DATA[34] => Mux~1.IN99
ROM_DATA[35] => Mux~0.IN99
ROM_DATA[36] => Mux~3.IN95
ROM_DATA[37] => Mux~2.IN95
ROM_DATA[38] => Mux~1.IN95
ROM_DATA[39] => Mux~0.IN95
ROM_DATA[40] => Mux~3.IN91
ROM_DATA[41] => Mux~2.IN91
ROM_DATA[42] => Mux~1.IN91
ROM_DATA[43] => Mux~0.IN91
ROM_DATA[44] => Mux~3.IN87
ROM_DATA[45] => Mux~2.IN87
ROM_DATA[46] => Mux~1.IN87
ROM_DATA[47] => Mux~0.IN87
ROM_DATA[48] => Mux~3.IN83
ROM_DATA[49] => Mux~2.IN83
ROM_DATA[50] => Mux~1.IN83
ROM_DATA[51] => Mux~0.IN83
ROM_DATA[52] => Mux~3.IN79
ROM_DATA[53] => Mux~2.IN79
ROM_DATA[54] => Mux~1.IN79
ROM_DATA[55] => Mux~0.IN79
ROM_DATA[56] => Mux~3.IN75
ROM_DATA[57] => Mux~2.IN75
ROM_DATA[58] => Mux~1.IN75
ROM_DATA[59] => Mux~0.IN75
ROM_DATA[60] => Mux~3.IN71
ROM_DATA[61] => Mux~2.IN71
ROM_DATA[62] => Mux~1.IN71
ROM_DATA[63] => Mux~0.IN71
ROM_DATA[64] => Mux~3.IN67
ROM_DATA[65] => Mux~2.IN67
ROM_DATA[66] => Mux~1.IN67
ROM_DATA[67] => Mux~0.IN67
ROM_DATA[68] => Mux~3.IN63
ROM_DATA[69] => Mux~2.IN63
ROM_DATA[70] => Mux~1.IN63
ROM_DATA[71] => Mux~0.IN63
ROM_DATA[72] => Mux~3.IN59
ROM_DATA[73] => Mux~2.IN59
ROM_DATA[74] => Mux~1.IN59
ROM_DATA[75] => Mux~0.IN59
ROM_DATA[76] => Mux~3.IN55
ROM_DATA[77] => Mux~2.IN55
ROM_DATA[78] => Mux~1.IN55
ROM_DATA[79] => Mux~0.IN55
TCK => word_counter[3].CLK
TCK => word_counter[2].CLK
TCK => word_counter[1].CLK
TCK => word_counter[0].CLK
TCK => WORD_SR[3].CLK
TCK => WORD_SR[2].CLK
TCK => WORD_SR[1].CLK
TCK => WORD_SR[0].CLK
TCK => word_counter[4].CLK
SHIFT => word_counter~5.OUTPUTSELECT
SHIFT => word_counter~6.OUTPUTSELECT
SHIFT => word_counter~7.OUTPUTSELECT
SHIFT => word_counter~8.OUTPUTSELECT
SHIFT => word_counter~9.OUTPUTSELECT
SHIFT => WORD_SR~0.OUTPUTSELECT
SHIFT => WORD_SR~1.OUTPUTSELECT
SHIFT => WORD_SR~2.OUTPUTSELECT
SHIFT => WORD_SR~3.OUTPUTSELECT
UPDATE => clear_signal.IN0
USR1 => clear_signal.IN1
ENA => word_counter~10.OUTPUTSELECT
ENA => word_counter~11.OUTPUTSELECT
ENA => word_counter~12.OUTPUTSELECT
ENA => word_counter~13.OUTPUTSELECT
ENA => word_counter~14.OUTPUTSELECT
ENA => WORD_SR~4.OUTPUTSELECT
ENA => WORD_SR~5.OUTPUTSELECT
ENA => WORD_SR~6.OUTPUTSELECT
ENA => WORD_SR~7.OUTPUTSELECT
TDI => WORD_SR~0.DATAA
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE


|BOX|PLLU:u2
areset => altpll:altpll_component.areset
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|BOX|PLLU:u2|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= <UNC>
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>