box.tan.summary

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.992 ns
From           : DS0
To             : Q1[7]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.173 ns
From           : DATA_BUS_VALUE[7]
To             : DATA_BUS[7]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.503 ns
From           : altera_internal_jtag
To             : allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'PLLU:u2|altpll:altpll_component|_clk0'
Slack          : 4.923 ns
Required Time  : 100.01 MHz ( period = 9.999 ns )
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_datain_reg0
To             : allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|ram_block3a0~porta_memory_reg0
From Clock     : PLLU:u2|altpll:altpll_component|_clk0
To Clock       : PLLU:u2|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : 13.463 ns
Required Time  : 48.00 MHz ( period = 20.833 ns )
Actual Time    : 135.69 MHz ( period = 7.370 ns )
From           : CLK_COUNT_400HZ[8]
To             : CLK_COUNT_400HZ[5]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 95.13 MHz ( period = 10.512 ns )
From           : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'auto_stp_external_clock_0'
Slack          : N/A
Required Time  : None
Actual Time    : 130.36 MHz ( period = 7.671 ns )
From           : sld_signaltap:BOX|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_0id:auto_generated|safe_q[1]
To             : sld_signaltap:BOX|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_tjb2:auto_generated|ram_block1a0~porta_datain_reg0
From Clock     : auto_stp_external_clock_0
To Clock       : auto_stp_external_clock_0
Failed Paths   : 0

Type           : Clock Hold: 'CLK'
Slack          : 1.040 ns
Required Time  : 48.00 MHz ( period = 20.833 ns )
Actual Time    : N/A
From           : next_command.reset3
To             : next_command.reset3
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Hold: 'PLLU:u2|altpll:altpll_component|_clk0'
Slack          : 1.326 ns
Required Time  : 100.01 MHz ( period = 9.999 ns )
Actual Time    : N/A
From           : Q1[0]
To             : Q1[0]
From Clock     : PLLU:u2|altpll:altpll_component|_clk0
To Clock       : PLLU:u2|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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