bcd2.map.summary

verilogHDL 入门的小程序

Flow Status : Successful - Fri Jul 11 12:06:26 2008
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : BCD2
Top-level Entity Name : BCD2
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 5
Total pins : 13
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0